NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 329
NH82801DB S L8DE
Manufacturer Part Number
NH82801DB S L8DE
Description
Manufacturer
Intel
Datasheet
1.NH82801DB_S_L8DE.pdf
(587 pages)
Specifications of NH82801DB S L8DE
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9.4.9
Intel
®
82801DB ICH4 Datasheet
ELCR1—Master Controller Edge/Level Triggered Register
Offset Address:
Default Value:
In edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. In level mode
(bit[x] = 1), the interrupt is recognized by a high level. The cascade channel, IRQ2, the heart beat
timer (IRQ0), and the keyboard controller (IRQ1), cannot be put into level mode.
Bit
4:3
1:0
Bit
2:0
2
7
6
5
4
3
IRQ7 ECL — R/W.
0 = Edge.
1 = Level.
IRQ6 ECL — R/W.
0 = Edge.
1 = Level.
IRQ5 ECL — R/W.
0 = Edge.
1 = Level.
IRQ4 ECL — R/W.
0 = Edge.
1 = Level.
IRQ3 ECL — R/W.
0 = Edge.
1 = Level.
Reserved. Must be 0.
OCW3 Select — WO. When selecting OCW3, bits 4:3 = 01
Poll Mode Command — WO.
0 = Disable. Poll Command is not issued.
1 = Enable. The next I/O read to the interrupt controller is treated as an interrupt acknowledge cycle.
Register Read Command — WO. These bits provide control for reading the In-Service Register
(ISR) and the Interrupt Request Register (IRR). When bit 1=0, bit 0 will not affect the register read
selection. When bit 1=1, bit 0 selects the register status returned following an OCW3 read. If bit 0=0,
the IRR will be read. If bit 0=1, the ISR will be read. Following ICW initialization, the default OCW3
port address read will be “read IRR”. To retain the current selection (read ISR or read IRR), always
write a 0 to bit 1 when programming this register. The selected register can be read repeatedly
without reprogramming OCW3. To select a new status register, OCW3 must be reprogrammed prior
to attempting the read.
00 = No Action
01 = No Action
10 = Read IRQ Register
11 = Read IS Register
An encoded byte is driven onto the data bus, representing the highest priority level requesting
service.
4D0h
00h
Description
Description
Attribute:
Size:
LPC Interface Bridge Registers (D31:F0)
R/W
8 bits
329
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