NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 146

• Manufacturer Part Number: NH82801DB S L8DE
• Manufacturer: Intel

Specifications of NH82801DB S L8DE

• Lead Free Status / RoHS Status: Compliant

Functional Description
5.12.7.4
5.12.7.5
5.12.8
5.12.8.1
146
Table 5-44. Transitions Due to Power Button
Note: The 4-second PWRBTN# assertion should only be used if a system lock-up has occurred. The
Processor-Initiated Passive Cooling (Via Programmed Duty Cycle on
STPCLK#)
Using the THTL_EN and THTL_DTY bits, the ICH4 can force a programmed duty cycle on the
STPCLK# signal. This reduces the effective instruction rate of the processor and cut its power
consumption and heat generation.
Active Cooling
Active cooling involves fans. The GPIO signals from the ICH4 can be used to turn on/off a fan.
Event Input Signals and Their Usage
The ICH4 has various input signals that trigger specific events. This section describes those signals
and how they should be used.
PWRBTN# - Power Button
The ICH4 PWRBTN# signal operates as a “Fixed Power Button” as described in the ACPI
specification. PWRBTN# signal has a 16 ms de-bounce on the input. The state transition
descriptions are included in
pressed (but after the debounce logic), and does not depend on when the Power Button is released.
Power Button Override Function
If PWRBTN# is observed active for at least four consecutive seconds, then the state machine
should unconditionally transition to the G2/S5 state, regardless of present state (S0–S4). In this
case, the transition to the G2/S5 state should not depend on any particular response from the
processor (e.g., a Stop-Grant cycle), nor any similar dependency from any other subsystem.
New: A power button override will force a transition to S5, even if PWROK is not active
The PWRBTN# status is readable to check if the button is currently being pressed or has been
released. The status is taken after the de-bounce, and is readable via the PWRBTN_LVL bit.
4-second timer starts counting when the ICH4 is in a S0 state. If the PWRBTN# signal is asserted
and held active when the system is in a suspend state (S1–S5), the assertion causes a wake event.
Once the system has resumed to the S0 state, the 4-second timer starts.
Present
S1–S5
S0–S4
S0/Cx
State
G3
PWRBTN# held low for
at least 4 consecutive
PWRBTN# goes low
PWRBTN# goes low
PWRBTN# pressed
seconds
Event
Table
5-44. Note that the transitions start as soon as the PWRBTN# is
Wake Event. Transitions to
Unconditional transition to S5
(depending on SCI_EN)
SMI# or SCI generated
Transition/Action
S0 state.
None
state.
Intel
Software will typically initiate a
Sleep state.
Standard wakeup
No effect since no power.
Not latched nor detected.
No dependence on processor
(e.g., Stop-Grant cycles) or any
other subsystem.
®
82801DB ICH4 Datasheet
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