NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 290
NH82801DB S L8DE
Manufacturer Part Number
NH82801DB S L8DE
Description
Manufacturer
Intel
Datasheet
1.NH82801DB_S_L8DE.pdf
(587 pages)
Specifications of NH82801DB S L8DE
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Hub Interface to PCI Bridge Registers (D30:F0)
8.1.31
290
ERR_STS—Error Status Register (HUB-PCI—D30:F0)
Offset Address:
Default Value:
Lockable:
This register records the cause of system errors in Device 30. The actual assertion of SERR# is
enabled via the PCI Command register.
Bit
7:3
1:0
2
Reserved
SERR# Due to Received Target Abort (SERR_RTA) — R/W.
0 = Software clears this bit by writing a 1 to it.
1 = The Intel
Reserved
also generate an SERR# when SERR_RTA is set.
92h
00h
No
®
ICH4 sets this bit when the ICH4 receives a target abort. If SERR_EN, the ICH4 will
Description
Attribute:
Size:
Power Well:
Intel
R/W
8 bit
Core
®
82801DB ICH4 Datasheet
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