NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 334
NH82801DB S L8DE
Manufacturer Part Number
NH82801DB S L8DE
Description
Manufacturer
Intel
Datasheet
1.NH82801DB_S_L8DE.pdf
(587 pages)
Specifications of NH82801DB S L8DE
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LPC Interface Bridge Registers (D31:F0)
9.5.7
9.5.8
a
9.5.9
a
334
VER—Version Register
Index Offset:
Default Value:
Each I/O APIC contains a hardwired Version Register that identifies different implementation of
APIC and their versions. The maximum redirection entry information also is in this register, to let
software know how many interrupt are supported by this APIC.
ARBID—Arbitration ID Register
Index Offset:
Default Value:
This register contains the bus arbitration priority for the APIC. If APIC Clock is running, this
register is loaded whenever the APIC ID register is loaded. A rotating priority scheme is used for
APIC bus arbitration. The winner of the arbitration becomes the lowest priority agent and assumes
an arbitration ID of 0.
BOOT_CONFIG—Boot Configuration Register
Index Offset:
Default Value:
This register is used to control the interrupt delivery mechanism for the APIC.
31:24
23:16
14:8
7:0
Bit
31:28
27:24
15
23:0
31:1
Bit
Bit
0
Reserved
Maximum Redirection Entries — RO. This is the entry number (0 being the lowest entry) of the
highest entry in the redirection table. It is equal to the number of interrupt input pins minus one and
is in the range 0 through 239. In the Intel
interrupts.
PRQ — RO. This bit is set to 1 to indicate that this version of the I/O APIC implements the IRQ
Assertion register and allows PCI devices to write to it to cause interrupts.
Reserved
Version — RO. This is a version number that identifies the implementation version.
Reserved
I/O APIC Identification — RO. This 4-bit field contains the I/O APIC Arbitration ID.
Reserved
Reserved
Delivery Type (DT) — R/W.
0 = Interrupt delivery mechanism is via the APIC serial bus (default).
1 = Interrupt delivery mechanism is a Processor System Bus message.
01h
00170002h
02h
00000000h
03h
00000000h
®
ICH4 this field is hardwired to 17h to indicate 24
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Intel
RO
32 bits
RO
32 bits
R/W
32 bits
®
82801DB ICH4 Datasheet
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