M393T5750EZA-CE6 Samsung Semiconductor, M393T5750EZA-CE6 Datasheet - Page 4

• Manufacturer Part Number: M393T5750EZA-CE6
• Manufacturer: Samsung Semiconductor

Specifications of M393T5750EZA-CE6

• Lead Free Status / RoHS Status: Compliant

1.0 DDR2 Registered DIMM Ordering Information
Note :
1. “Z” of Part number(11th digit) stands for Lead-Free products.
2. “3” of Part number(12th digit) stands for Dummy Pad PCB products.
3. “A” of Part number(12th digit) stands for Parity Register products.
2.0 Features
3.0 Address Configuration
RDIMM
M393T6553EZ3-CD5/CC
M393T6553EZA-CF7/E6
M393T2953EZ3-CD5/CC
M393T2953EZA-CF7/E6
M393T2950EZ3-CD5/CC
M393T2950EZA-CF7/E6
M393T5750EZ3-CD5/CC
M393T5750EZA-CF7/E6
Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.
• Performance range
• JEDEC standard V
• V
• 200 MHz f
• 4 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5, 6
• Programmable Additive Latency: 0, 1 , 2 , 3, 4 and 5
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/Nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination with selectable values(50/75/150 ohms or disable)
• Average Refresh Period 7.8us at lower than a T
• Serial presence detect with EEPROM
• DDR2 SDRAM Package: 60ball FBGA - 128Mx4/64Mx8
• All of products are Lead-Free and RoHS compliant
- Support High Temperature Self-Refresh rate enable feature
DDQ
128Mx4(512Mb) based Module
64Mx8(512Mb) based Module
CL-tRCD-tRP
Speed@CL3
Speed@CL4
Speed@CL5
Speed@CL6
Part Number
= 1.8V ± 0.1V
CK
Organization
for 400Mb/sec/pin, 267MHz f
DD
= 1.8V ± 0.1V Power Supply
F7(DDR2-800)
Density
512MB
512MB
1GB
1GB
1GB
1GB
2GB
2GB
6-6-6
533
667
800
-
CK
Organization
Row Address
for 533Mb/sec/pin, 333MHz f
128Mx72
128Mx72
128Mx72
128Mx72
256Mx72
256Mx72
64Mx72
64Mx72
CASE
A0-A13
A0-A13
85°C, 3.9us at 85°C < T
E6(DDR2-667)
128Mx4(K4T51043QE)*18EA
128Mx4(K4T51043QE)*18EA
128Mx4(K4T51043QE)*36EA
128Mx4(K4T51043QE)*36EA
64Mx8(K4T51083QE)*18EA
64Mx8(K4T51083QE)*18EA
64Mx8(K4T51083QE)*9EA
64Mx8(K4T51083QE)*9EA
Component Composition
5-5-5
400
533
667
-
4 of 26
Column Address
A0-A9,A11
CK
CASE
A0-A9
for 667Mb/sec/pin, 400MHz f
< 95 °C
D5(DDR2-533)
4-4-4
400
533
533
-
Number of Rank
Bank Address
BA0-BA1
BA0-BA1
1
1
2
2
1
1
2
2
CK
for 800Mb/sec/pin
CC(DDR2-400)
Rev. 1.4 August 2008
Parity Register
3-3-3
DDR2 SDRAM
400
400
-
-
O
X
X
O
X
O
X
O
Auto Precharge
A10
A10
30.00mm
30.00mm
30.00mm
30.00mm
30.00mm
30.00mm
30.00mm
30.00mm
Height
Units
Mbps
Mbps
Mbps
Mbps
CK