M393T5750EZA-CE6 Samsung Semiconductor, M393T5750EZA-CE6 Datasheet - Page 21

• Manufacturer Part Number: M393T5750EZA-CE6
• Manufacturer: Samsung Semiconductor

Specifications of M393T5750EZA-CE6

• Lead Free Status / RoHS Status: Compliant

13.4 Timing parameters by speed grade (DDR2-533 and DDR2-400)
(Refer to notes for informations related to this table at the component datasheet)
RDIMM
DQ output access time from CK/CK
DQS output access time from CK/CK
CK HIGH pulse width
CK LOW pulse width
CK half pulse period
Clock cycle time, CL=x
DQ and DM input hold time (differential strobe)
DQ and DM input setup time (differential strobe)
DQ and DM input hold time (single-ended strobe)
DQ and DM input setup time (single-ended strobe)
Control & Address input pulse width for each input
DQ and DM input pulse width for each input
Data-out high-impedance time from CK/CK
DQS(/DQS) low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ signals
DQ hold skew factor
DQ/DQS output hold time from DQS
DQS latching rising transitions to associated clock edges
DQS input HIGH pulse width
DQS input LOW pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
MRS command to ODT update delay
Write postamble
Write preamble
Address and control input hold time
Address and control input setup time
Read preamble
Read postamble
Active to active command period for 1KB page size products
Active to active command period for 2KB page size products
Parameter
tAC
tDQSCK
tCH
tCL
tHP
tCK
tDH(base)
tDS(base)
tDH1(base)
tDS1(base)
tIPW
tDIPW
tHZ
tLZ(DQS)
tLZ(DQ)
tDQSQ
tQHS
tQH
tDQSS
tDQSH
tDQSL
tDSS
tDSH
tMRD
tMOD
tWPST
tWPRE
tIH(base)
tIS(base)
tRPRE
tRPST
tRRD
tRRD
Symbol
21 of 26
Min(tCL, tCH)
2* tAC(min)
tHP - tQHS
tAC(min)
3750
-0.25
min
0.45
0.45
0.35
0.35
-500
-450
225
100
0.35
375
250
-25
-25
0.6
0.2
0.2
0.4
0.35
0.9
0.4
7.5
10
2
0
x
x
x
DDR2-533
tAC(max)
tAC(max)
tAC(max)
8000
max
0.55
0.55
0.25
500
450
300
400
0.6
1.1
0.6
12
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Min(tCL, tCH)
2* tAC(min)
tHP - tQHS
tAC(min)
5000
-0.25
-600
-500
0.45
0.45
0.35
0.35
0.35
min
275
150
0.35
475
350
x14
0.6
0.2
0.2
0.4
0.9
0.4
7.5
25
25
10
x
x
2
0
DDR2-400
tAC(max)
tAC(max)
tAC(max)
max
0.55
0.55
8000
0.25
600
500
350
450
0.6
1.1
0.6
12
Rev. 1.4 August 2008
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
DDR2 SDRAM
Units
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ns
ps
ps
ns
ns
6,7,8,21,28
6,7,8,20,28
6,7,8,26
6,7,8,25
5,7,9,23
5,7,9,22
Notes
11,12
15
18
18
18
13
12
10
19
19
4
4