M393T5750EZA-CE6 Samsung Semiconductor, M393T5750EZA-CE6 Datasheet
M393T5750EZA-CE6
Specifications of M393T5750EZA-CE6
Related parts for M393T5750EZA-CE6
M393T5750EZA-CE6 Summary of contents
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... RDIMM DDR2 Registered SDRAM MODULE 240pin Registered Module based on 512Mb E-die INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER- WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL- OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS " ...
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... M393T2953EZ3 / M393T2953EZA : 1GB(64Mx8 *18) Module 11.5 M393T2950EZ3 / M393T2950EZA : 1GB(128Mx4 *18) Module 11.6 M393T2950EZ3 / M393T2950EZA : 1GB(128Mx4 *18) Module 11.7 M393T5750EZ3 / M393T5750EZA : 2GB(128Mx4 *36) Module 11.8 M393T5750EZ3 / M393T5750EZA : 2GB(128Mx4 *36) Module 12.0 Input/Output Capacitance .......................................................................................................18 13.0 Electrical Characteristics & AC Timing for DDR2-800/667/533/400 .....................................18 13.1 Refresh Parameters by Device Density 13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin 13 ...
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RDIMM Revision History Revision Month Year 1.0 April 2007 1.1 May 2007 1.2 June 2007 1.3 July 2008 1.4 August 2008 - Initial Release - Corrected Typo - Corrected Typo - Applied JEDEC update(JESD79-2E timing table - VLP ...
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... M393T2950EZ3-CD5/CC 1GB M393T2950EZA-CF7/E6 1GB M393T5750EZ3-CD5/CC 2GB M393T5750EZA-CF7/E6 2GB Note : 1. “Z” of Part number(11th digit) stands for Lead-Free products. 2. “3” of Part number(12th digit) stands for Dummy Pad PCB products. 3. “A” of Part number(12th digit) stands for Parity Register products. 2.0 Features • ...
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... RESET (Pin 18) is connected to both OE of PLL and Reset of register. 2. The Test pin (Pin 102) is reserved for bus analysis probes and is not connected on normal memory modules (DIMMs) 3. NC/Err_Out ( Pin 55) and NC/Par_In (Pin 68) are for optional function to check address and command parity. ...
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RDIMM 6.0 Input/Output Functional Description Symbol Type CK0 Input Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL. CK0 Input Negative line of the differential pair of system clock inputs that drives ...
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... RDIMM 7.0 Functional Block Diagram 7.1 512MB, 64Mx72 Module - M393T6553EZ3/M393T6553EZA RS0 DQS0 DQS0 DM0/DQS9 NC/DQS9 DM/ NU/ CS DQS DQS RDQS RDQS DQ0 I/O 0 DQ1 I DQ2 I/O 2 DQ3 I/O 3 DQ4 I/O 4 DQ5 I/O 5 DQ6 I/O 6 DQ7 I/O 7 DQS1 DQS1 DM1/DQS10 NC/DQS10 DM/ NU/ CS DQS DQS ...
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... RDIMM 7.2 1GB, 128Mx72 Module - M393T2953EZ3/M393T2953EZA (populated as 2 rank of x8 DDR2 SDRAMs) RS1 RS0 DQS0 DQS0 DM0/DQS9 NC/DQS9 DM/ NU/ CS DQS DQS RDQS RDQS DQ0 I/O 0 DQ1 D0 I/O 1 DQ2 I/O 2 DQ3 I/O 3 DQ4 I/O 4 DQ5 I/O 5 DQ6 I/O 6 DQ7 I/O 7 DQS1 DQS1 ...
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... RDIMM 7.3 1GB, 128Mx72 Module - M393T2950EZ3/M393T2950EZA (populated as 1 rank of x4 DDR2 SDRAMs RS0 DQS0 DQS0 DM CS DQS DQS DQ0 I/O 0 DQ1 I DQ2 I/O 2 DQ3 I/O 3 DQS1 DQS1 DM CS DQS DQS DQ8 I/O 0 DQ9 D1 I/O 1 DQ10 I/O 2 DQ11 I/O 3 DQS2 DQS2 DM CS DQS DQS ...
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... SA0 SA1 SA2 I DDSPD DDQ DM CS DQS DQS I I/O 1 D35 REF I Signals for Address and Command Parity Function (M393T5750EZA) Register A Register PPO PAR_IN PAR_IN QERR The resistors on Par_In, A13, A14, A15, BA2 and the signal line of Err_Out refer to the section: "Register Options for Unused Address inputs" ...
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RDIMM 8.0 Absolute Maximum DC Ratings Symbol Parameter Voltage on V pin relative Voltage on V pin relative DDQ DDQ Voltage on V pin relative DDL DDL Voltage on ...
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RDIMM 9.2 Operating Temperature Condition Symbol T Operating Temperature OPER Note : 1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2 standard ...
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RDIMM 10.0 IDD Specification Parameters Definition (IDD values are for full operating range of Voltage and Temperature) Symbol Operating one bank active-precharge current; IDD0 tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH HIGH between ...
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... IDD2N IDD3P-F IDD3P-S IDD3N IDD4W IDD4R IDD5B IDD6* IDD7 * IDD6 = DRAM current + standby current of PLL and Register ** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. E6(667@CL=5) D5(533@CL=4) 765 675 855 810 72 72 315 ...
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... IDD3P-F IDD3P-S IDD3N IDD4W IDD4R IDD5B IDD6* IDD7 * IDD6 = DRAM current + standby current of PLL and Register ** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. E6(667@CL=5) D5(533@CL=4) 1,125 1,035 1,215 1,170 144 144 630 ...
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... IDD4R 3,130 IDD5B 2,900 IDD6* 144 IDD7 4,900 * IDD6 = DRAM current + standby current of PLL and Register ** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. E6(667@CL=5) D5(533@CL=4) 1,350 1,530 144 630 720 540 216 ...
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... IDD5B 2,790 IDD6* 288 IDD7 4,590 * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. 11.8 M393T5750EZ3 / M393T5750EZA : 2GB(128Mx4 *36) Module - considering Register and PLL current value Symbol F7(800@CL=6) IDD0 3,270 IDD1 3,590 IDD2P ...
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... CASE DDR2-667(E6 max min max min - 3. 70000 45 70000 DDR2 SDRAM (V =1.8V DDQ Max Min Max Min M393T2950EZ3 M393T5750EZ3 M393T2950EZA M393T5750EZA 512Mb 1Gb 2Gb 75 105 127.5 195 7.8 7.8 7.8 7.8 3.9 3.9 3.9 3.9 DDR2-533(D5) DDR2-400(CC max min max ...
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RDIMM 13.3 Timing parameters by speed grade (DDR2-800 and DDR2-667) (Refer to notes for informations related to this table at the component datasheet) Parameter DQ output access time from CK/CK DQS output access time from CK/CK Average clock HIGH pulse ...
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RDIMM Parameter Four Activate Window for 1KB page size products Four Activate Window for 2KB page size products CAS to CAS command delay Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Internal ...
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RDIMM 13.4 Timing parameters by speed grade (DDR2-533 and DDR2-400) (Refer to notes for informations related to this table at the component datasheet) Parameter DQ output access time from CK/CK DQS output access time from CK/CK CK HIGH pulse width ...
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RDIMM Parameter Four Activate Window for 1KB page size products Four Activate Window for 2KB page size products CAS to CAS command delay Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Internal ...
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... RDIMM 14.0 Physical Dimensions 14.1 64Mbx8 based 64Mx72 Module (1 Rank) 63.00 5.00 4.00 2.50 1.50±0.10 Detail A The used device is 64M x8 DDR2 SDRAM, FBGA. DDR2 SDRAM Part NO : K4T51083QE - M393T6553EZ3 / M393T6553EZA 133.35 PLL A B 55.00 4.00 0.80±0.05 3.80 0.20 1.00 Detail B ...
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... RDIMM 14.2 64Mbx8/128Mbx4 based 128Mx72 Module (2/1 Ranks) - M393T2953EZ3 / M393T2953EZA / M393T2950EZ3 / M393T2950EZA 63.00 5.00 4.00 2.50 1.50±0.10 Detail A The used device is 64M x8 / 128M x4 DDR2 SDRAM, FBGA. DDR2 SDRAM Part NO : K4T51083QE / K4T51043QE 133.35 PLL A B 55.00 4.00 0.80±0.05 3.80 0.20 1 ...
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... RDIMM 14.3 128Mbx4 based 256Mx72 Module (2 Ranks) 63.00 5.00 4.00 2.50 1.50±0.10 Detail A The used device is 128M x4 DDR2 SDRAM, FBGA. DDR2 SDRAM Part NO : K4T51043QE - M393T5750EZ3/M393T5750EZA 133.35 PLL A B 55.00 4.00 0.80±0.05 3.80 0.20 1.00 Detail DDR2 SDRAM Units : Millimeters 4 ...
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RDIMM 15.0 240 Pin DDR2 Registered DIMM Clock Topology CK0 120 ohms CK0 120 ohms C Note: 1. The clock delay from the input of the PLL clock to the input of any DDR2 SDRAM or register will be set ...