NAND08GW3B2CN6E NUMONYX, NAND08GW3B2CN6E Datasheet - Page 24

• Manufacturer Part Number: NAND08GW3B2CN6E
• Description: 8GBIT SLC NAND FLASH TSOP
• Manufacturer: NUMONYX

Specifications of NAND08GW3B2CN6E

• Cell Type: NAND
• Density: 8Gb
• Access Time (max): 25us
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 30b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 1G
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Compliant

Device operations
Figure 8.
6.2
24/72
RB
I/O
W
R
Row Add 1,2,3
Code
Cmd
00h
Random data output during sequential data output
Cache read
The cache read operation improves the read throughput by reading data using the cache
register. As soon as the user starts to read one page, the device automatically loads the
next page into the cache register.
A Read Page command, as defined in
first Read Cache command in a read cache sequence. Once the Read Page command
execution is terminated, the Cache Read command can be issued as follows:
1.
2.
The two commands can be used interchangeably, in any order. When there are no more
pages are to be read, the final page is copied into the cache register by issuing the Exit
Cache Read command. A Read Cache command must not be issued after the last page of
the device is read. Data output only starts after issuing the 31h command for the first time.
See
operation
5 Add cycles
Figure 9: Cache read (sequential) operation
Address
Issue a Sequential Cache Read command to copy the next page in sequential order to
the cache register
Issue a Random Cache Read command to copy the page addressed in this command
to the cache register.
Inputs
(Read Busy time)
Col Add 1,2
for examples of the two sequences.
tBLBH1
Code
30h
Main Area
Cmd
Busy
Data Output
Spare
Area
tRHWL
Section 6.1.1: Random
Code
Cmd
05h
Col Add 1,2
2 Add cycles
Address
and
Inputs
Figure 10: Cache read (random)
Code
NAND04G-B2D, NAND08G-BxC
E0h
Cmd
Main Area
read, is issued prior to the
Data Output
Spare
Area
ai08658b