NAND08GW3B2CN6E NUMONYX, NAND08GW3B2CN6E Datasheet
NAND08GW3B2CN6E
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NAND08GW3B2CN6E Summary of contents
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... ECC) – 10 years data retention RoHS compliant packages Table 1. Device summary Reference NAND04G-B2D NAND08G-BxC 1. x16 organization only available for MCP products. Rev 9 NAND04G-B2D NAND08G-BxC TSOP48 (N) LGA Part number NAND04GR3B2D NAND04GW3B2D (1) NAND04GR4B2D (1) NAND04GW4B2D NAND08GR3B2C, NAND08GW3B2C (1) NAND08GR4B2C (1) NAND08GW4B2C NAND08GR3B4C NAND08GW3B4C www.numonyx.com 1/72 1 ...
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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Concurrent operations and extended read status . . . . . . . . . . . . . . . . 45 8 Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9 Software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.1 Bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.2 NAND flash memory failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.3 Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.4 Wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.5 Error correction code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10 Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 49 Sequential input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Random data input in page ...
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Contents 11 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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NAND04G-B2D, NAND08G-BxC List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures List of figures Figure 1. Logic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Each block can be programmed and erased up to 100,000 cycles with ECC (error correction code) on. To extend the lifetime of NAND flash devices, the implementation of an ECC is mandatory. A write protect pin is available to provide hardware protection against program and erase operations ...
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... These security features are subject to an NDA (non-disclosure agreement) and are, therefore, not described in the datasheet. For more details about them, contact your nearest Numonyx sales office. For information on how to order these options, refer to scheme. Devices are shipped from the factory with block 0 always valid and the memory content bits, in valid blocks, erased to ’ ...
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... Command Interface E Logic WP R Command Register Figure 2. Logic diagram P/E/R Controller, High Voltage Generator I/O0-I/O7 (x8/x16) E I/O8-I/O15 (x16 NAND FLASH Description NAND Flash Memory Array Page Buffer Cache Register Y Decoder I/O Buffers & Latches I/O0-I/O7 (x8/x16) I/O8-I/O15 (x16) AI13167b AI13166b 9/72 ...
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Description Table 3. Signals names Signal I/O0-7 Data input/outputs, address inputs, or command inputs (x8/x16 devices) I/O8-15 Data input/outputs (x16 devices) AL Address Latch Enable CL Command Latch Enable E Chip Enable R Read Enable RB Ready/Busy (open-drain output) W ...
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... NAND04G-B2D, NAND08G-BxC Figure 3. TSOP48 connections for NAND04G-B2D and NAND08G-BxC NAND FLASH Description I/O7 I/O6 I/O5 I/ I/O3 I/O2 I/O1 I/ AI13168b 11/72 ...
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Description Figure 4. ULGA52 connections for NAND04G-B2D and NAND08G-B2C devices 12/ ...
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NAND04G-B2D, NAND08G-BxC Figure 5. ULGA52 connections for the NAND08G-B4C devices ...
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... In x16 devices, the pages are split into a 1024-word main area and a spare area of 32 words. Refer to Bad blocks In x8 devices, the NAND flash 2112-byte/1056-word page devices may contain bad blocks, which are blocks that contain one or more invalid bits whose reliability is not guaranteed. Additional bad blocks may develop during the lifetime of the device. ...
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NAND04G-B2D, NAND08G-BxC Figure 6. Memory array organization Plane = 2048 blocks, block = 64 pages, page = 2112 bytes (2048 + 64) Main area Block Page 2048 bytes Page buffer, 2112 bytes 2048 bytes Plane = 2048 blocks, block = ...
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Signals description 3 Signals description See Figure 2: Logic diagram connected to this device. 3.1 Inputs/outputs (I/O0-I/O7) Input/outputs input the selected address, output the data during a read operation, or input a command or data during a ...
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NAND04G-B2D, NAND08G-BxC 3.7 Write enable (W) The Write Enable input, W, controls writing to the command interface, input address and data latches. Both addresses and data are latched on the rising edge of Write Enable. During power-up and power-down a ...
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Bus operations 4 Bus operations There are six standard bus operations that control the memory, as described in this section. SeeTable 5: Bus operations Typically, glitches of less than Chip Enable, Write Enable, and Read Enable are ...
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NAND04G-B2D, NAND08G-BxC If the Read Enable pulse frequency is lower then 33 MHz (t output data is latched on the rising edge of Read Enable signal (see For higher frequencies (t used. In this mode, data output bus operations are ...
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Bus operations Table 7. Address insertion (x16 devices) Bus I/O7 (1) cycle A18 th 4 A26 Any additional address input cycles are ignored. 2. A29 is ...
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NAND04G-B2D, NAND08G-BxC 5 Command set All bus write operations to the device are interpreted by the command interface. The commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when the command Latch Enable signal ...
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Device operations 6 Device operations This section provides details of the device operations. 6.1 Read memory array At power-up the device defaults to read mode. To enter read mode from another mode, the Read command must be issued (see 6.1.1 ...
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NAND04G-B2D, NAND08G-BxC Figure 7. Read operations I/O Address Input 00h Command Code tBLBH1 30h Data Output (sequentially) Command Busy Code Device operations ai12469 23/72 ...
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Device operations Figure 8. Random data output during sequential data output tBLBH1 (Read Busy time Address 30h I/O 00h Inputs Cmd Cmd Code Code 5 Add cycles Row Add 1,2,3 Col Add 1,2 Main Area 6.2 Cache ...
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NAND04G-B2D, NAND08G-BxC After the Sequential Cache Read or Random Cache Read command has been issued, the Ready/Busy signal goes Low and the status register bits are set to SR5 =' 0' and SR6 ='0' for a period of cache read ...
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Device operations 6.3 Page program The page program operation is the standard operation to program data to the memory array. Generally, the page is programmed sequentially, however, the device does support random input within a page recommended to ...
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NAND04G-B2D, NAND08G-BxC Figure 11. Page program operation RB I/O 80h Page Program Setup Code Figure 12. Random data input during sequential data input RB Address I/O 80h Data Intput Inputs Cmd Code 5 Add cycles Row Add 1,2,3 Col Add ...
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Device operations 6.4 Multiplane page program The devices support multiplane page program, which enables the programming of two pages in parallel, one in each plane. A multiplane page program operation requires the following two steps: 1. The first step serially ...
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NAND04G-B2D, NAND08G-BxC Figure 13. Multiplane page program waveform RB 1 I/O Address inputs 80h A0-A11 = Valid Page Program setup code A12-A17 = set to 'Low' A18 = set to 'Low' A19-A28 = set to 'Low' 1) The same row ...
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Device operations operation is particularly useful when a portion of a block is updated and the rest of the block needs to be copied to the newly assigned block. The NAND04G-B2D and NAND08G-BxC devices feature automatic EDC (error detection code) ...
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NAND04G-B2D, NAND08G-BxC Figure 15. Copy back program (with readout of data) Source I/O 00h Add Inputs Read Code tBLBH1 (Read Busy time) RB Figure 16. Page copy back program with random data input Source I/O 35h 00h Add Inputs Read ...
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Device operations Figure 17. Multiplane copy back program Read Read code code Add. 5 I/O 35h 00h 00h cycles Col. Add Row Add Source address on 1st plane Source address on 2nd plane tBLBH1 (Read ...
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NAND04G-B2D, NAND08G-BxC An erase operation consists of the following three steps (refer to 1. One bus cycle is required to set up the Block Erase command. Only addresses A18- A28 are used; all other address inputs are ignored 2. Three ...
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Device operations 6.8 Multiplane block erase The multiplane block erase operation allows the erasure of two blocks in parallel, one in each plane. This operation consists of the following three steps (refer to erase bus cycles are required ...
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NAND04G-B2D, NAND08G-BxC 6.9 Error detection code (EDC) The EDC (error detection code) is performed automatically during all program operations. It starts immediately after the device becomes busy. The EDC detects 1 single bit error per EDC unit. Each EDC unit ...
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Device operations Table 13. Address definition for EDC units (x16 devices) EDC unit Area name 1st 264-word EDC unit 2nd 264-word EDC unit 3rd 264-word EDC unit 4th 264-word EDC unit 6.10 Reset The Reset command is used to reset ...
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NAND04G-B2D, NAND08G-BxC 6.11.2 P/E/R controller and cache ready/busy bit (SR6) Status register bit SR6 has two different functions depending on the current operation. During cache operations, SR6 acts as a cache ready/busy bit, which indicates whether the cache register is ...
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... Device operations 6.12 Read status enhanced In NAND flash devices with multiplane architecture possible to independently read the status register of a single plane using the Read Status Enhanced command. If the error bit of the status register, SR0, reports an error during or after a multiplane operation, the Read Status Enhanced command is used to know which of the two planes contains the page that failed the operation ...
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NAND04G-B2D, NAND08G-BxC 6.14 Read electronic signature The devices contain a manufacturer code and device code. The following three steps are required to read these codes: 1. One bus write cycle to issue the Read Electronic Signature command (90h) 2. One ...
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Device operations Table 18. Electronic signature byte 4 I/O I/O1-I/O0 (without spare area) Spare area size I/O2 (byte/512 byte) Minimum sequential access I/O7, I/O3 I/O5-I/O4 (without spare area) I/O6 Table 19. Electronic signature byte 5 I/O I/O1 - I/O0 I/O3 ...
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... Read ONFI signature To recognize NAND flash devices that are compatible with the ONFI 1.0 command set, the Read Electronic Signature can be issued, followed by an address of 20h. The next four bytes output is the ONFI signature, which is the ASCII encoding of the ‘ONFI’ word. Reading beyond four bytes produces indeterminate values ...
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Device operations Table 21. Parameter page data structure Byte O/M 0-3 4-5 6-7 8-9 10-31 32-43 44-63 64 65-66 67-79 80-83 84-85 86-89 90-91 92-95 42/72 (1) Parameter page signature – Byte 0: 4Fh, ‘O’ M – Byte 1: 4Eh, ...
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NAND04G-B2D, NAND08G-BxC Table 21. Parameter page data structure (continued) Byte O/M 96-99 100 101 102 103-104 105-106 107 108-109 110 111 112 113 114 115-127 128 (1) M Number of blocks per logical unit (LUN) M Number of logical units ...
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Device operations Table 21. Parameter page data structure (continued) Byte O/M 129-130 131-132 133-134 135-136 137-138 139-163 164-165 166-253 254-255 256-511 512-767 768 optional mandatory. 44/72 (1) Timing mode support Bit 6 to bit 15 ...
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NAND04G-B2D, NAND08G-BxC 7 Concurrent operations and extended read status The NAND08G-BxC devices are composed of two 4-Gbit dice stacked together. This configuration allows the devices to support concurrent operations, which means that while performing an operation in one die (erase, ...
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... Implementation of a garbage collection, a wear-leveling algorithm and an error correction code is recommended. To help integrate a NAND memory into an application, Numonyx provides a file system OS native reference software, which supports the basic commands of file management. Contact the nearest Numonyx sales office for more details. ...
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... NAND04G-B2D, NAND08G-BxC 9.2 NAND flash memory failure modes Over the lifetime of the device bad blocks may develop. To implement a highly reliable system, the possible failure modes must be considered. Program/erase failure In this case, the block has to be replaced by copying the data to a valid block. These additional bad blocks can be identified because attempts to program or erase them gives errors in the status register ...
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... Error correction code Users must implement an error correction code (ECC) to identify and correct errors in the data stored in the NAND flash memories. The ECC implemented must be able to correct 1 bit for every 512 bytes. Sensible data stored in the spare area must be covered by ECC as well ...
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... Multiplane erase busy time (t IEBSY Cache read busy time (t ) RCBSY Program/erase cycles per block (with ECC) Data retention Program and erase times and endurance cycles Min 100,000 10 NAND flash Unit Typ Max 200 700 200 700 250 800 ...
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Maximum ratings 11 Maximum ratings Stressing the device above the ratings listed in cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the ...
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... Input/output capacitances double in stacked devices. Parameter 1.8 V device ) 3 V device Grade Grade 6 1.8 V device ) (1 TTL GATE device ref (1) Parameter Test condition (2) IL and C are not 100% tested. IN I/O DC and AC parameters NAND flash Units Min Max 1.7 1.95 V 2.7 3 °C – 8.35 kΩ ...
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... Standby and leakage currents refer to a single die device. For a multiple die device, their value must be multiplied for the number of dice of the stacked device, while the active power consumption depends on the number of dice concurrently executing different operations. 52/72 NAND Flash C L GND (1) ...
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NAND04G-B2D, NAND08G-BxC Table 29. DC characteristics (3 V devices) Symbol Parameter I DD1 Operating I current DD2 I DD3 Standby current (TTL) I DD4 I Standby current (CMOS) DD5 I Input leakage current LI I Output leakage current LO V ...
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DC and AC parameters Table 31. AC characteristics for operations Symbol Alt. t Address Latch Low to Read ALLRL1 t AR Enable Low t ALLRL2 t t Ready/Busy High to Read Enable Low BHRL RR t BLBH1 t t BLBH2 ...
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NAND04G-B2D, NAND08G-BxC Figure 24. Command latch AC waveforms CL tCLHWH (CL Setup time) tELWH H(E Setup time tALLWH (ALSetup time) AL I/O Figure 25. Address latch AC waveforms CL tELWH (E Setup time) E tWLWH W tWHWL tALHWH ...
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DC and AC parameters Figure 26. Data input latch AC waveforms CL E tALLWH (ALSetup time) AL tWLWH W (Data Setup time) I/O 1. The last data input is the 2112th. Figure 27. Sequential data output after read AC waveforms ...
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NAND04G-B2D, NAND08G-BxC Figure 28. Sequential data output after read AC waveforms (EDO mode) E tRLRH R tELQV tRLQV (R Accesstime) I/O tBHRL EDO mode, CL and AL are Low applicable for frequencies high ...
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DC and AC parameters Figure 30. Read status enhanced waveform I/O 0-7 78h Address 1 Figure 31. Read electronic signature AC waveform I/O 90h Read Electronic Signature Command 1. Refer to ...
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NAND04G-B2D, NAND08G-BxC Figure 32. Read ONFI signature waveform I/O 90h Read Electronic Signature command tALLRL1 tRLQV (Read ES access time) 4Fh 20h 4Eh 1st cycle address DC and AC parameters 46h 49h XXh ai13178b 59/72 ...
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DC and AC parameters Figure 33. Page read operation AC waveform CL E tWLWL Add.N Add.N Add.N I/O 00h cycle 1 cycle 2 cycle 3 Command Address N Input Code 60/72 tWHBL tALLRL2 tWHBH tRLRH tBLBH1 ...
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NAND04G-B2D, NAND08G-BxC Figure 34. Page program AC waveform CL E tWLWL (Write Cycle time Add.N Add.N I/O 80h cycle 1 cycle 2 RB Page Program Setup Code tWLWL tWHWH Add.N Add.N Add.N N cycle 4 cycle 5 ...
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DC and AC parameters Figure 35. Block erase AC waveform CL E tWLWL (Write Cycle time Add. I/O 60h cycle 1 RB Block Erase Block Address Input Setup Command Figure 36. Reset AC waveform ...
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NAND04G-B2D, NAND08G-BxC Figure 37. Program/erase enable waveform W tVHWH WP RB I/O 80h Program setup Figure 38. Program/erase disable waveform W tVLWH WP High RB I/O Program disable I High RB I/O 80h DC and ...
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DC and AC parameters Figure 39. Read parameter page waveform I/O0-7 ECh R/B 64/72 00h tBLBH1 NAND04G-B2D, NAND08G-BxC ... ... ai14409 ...
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NAND04G-B2D, NAND08G-BxC 12.1 Ready/busy signal electrical characteristics Figure 41, Figure 40 signal. The value required for the resistor R This is an example for 3 V devices: where I is the sum of the input currents of all the devices ...
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... DC and AC parameters Figure 42. Resistor value versus waveform timings for ready/busy signal °C. 12.2 Data protection The Numonyx NAND devices are designed to guarantee data protection during power transitions detection circuit disables all NAND operations the V range from V DD low ( guarantee hardware protection during power transitions as shown in the below IL figure ...
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... NAND04G-B2D, NAND08G-BxC 13 Package mechanical To meet environmental requirements, Numonyx offers these devices in RoHS compliant packages, which have a lead-free second-level interconnect. The category of second-level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...
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Package mechanical Figure 45. ULGA52 0.65 mm pitch, package outline FE1 Drawing is not to scale. Table 33. ULGA52 0.65 mm pitch, ...
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... F = RoHS compliant package, tape and reel packing 1. x16 organization only available for MCP products Note: Not all combinations are necessarily available. For a list of available devices of for further information on any aspect of these products, please contact your nearest Numonyx sales office. Ordering information NAND04GW3B2D N ...
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... Table 1, Table 2, Table – Added Figure 5: ULGA52 connections for the NAND08G-B4C devices. Changed VLKO value in 3 Applied Numonyx branding. Modified: Figure 6: Memory array Multiplane page program back program, Figure 19: Multiplane block Read status enhanced enable waveform, Figure 38: Program/erase disable and ...
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NAND04G-B2D, NAND08G-BxC Table 35. Document revision history (continued) Date 05-Jan-2010 09-Feb-2010 Revision Modified: EDC paragraph in Bad block management, Section 9.5: Error correction 8 back program. Removed Fig.23 Error detection. Removed Note 1 below Logic diagram, Table 3: Signals 9 ...
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... NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility Numonyx may make changes to specifications and product descriptions at any time, without notice. ...