ISP1507EBS,518 NXP Semiconductors, ISP1507EBS,518 Datasheet - Page 63

• Manufacturer Part Number: ISP1507EBS,518
• Description: RF Transceiver USB 2.0 ULPI TRNSCVR
• Manufacturer: NXP Semiconductors

Specifications of ISP1507EBS,518

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Power Supply Requirement: Single
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Compliant
• Other names: 935285498518 ISP1507EBS-T

NXP Semiconductors
Table 56.
V
ISP1507E_ISP1507F_1
Product data sheet
Symbol
t
t
t
t
Receiver timing
Differential receiver
t
t
PHZ
PLZ
PZH
PZL
PLH(rcv)
PHL(rcv)
CC
Fig 26. Rise time and fall time
Fig 28. Timing of TX_ENABLE to DP and DM
1.8 V
V
V
V
V
0 V
OH
OH
OL
= 3.0 V to 3.6 V; V
OL
logic
input
differential
data lines
0.9 V
Parameter
driver disable delay from
HIGH level
driver disable delay from
LOW level
driver enable delay to
HIGH level
driver enable delay to
LOW level
receiver propagation
delay (LOW to HIGH)
receiver propagation
delay (HIGH to LOW)
Dynamic characteristics: analog I/O pins (DP and DM)
t
HSR
10 %
15.1 ULPI timing
, t
FR
t
V
t
PZH
PZL
CRS
, t
LR
CC(I/O)
90 %
ULPI timing requirements are given in
mode only. All timing is measured with respect to the ISP1507 CLOCK pin. All signals are
clocked on the rising edge of CLOCK.
= 1.65 V to 1.95 V; T
V
V
OH
90 %
OL
+ 0.3 V
t
Conditions
TX_ENABLE to DP, DM;
see
TX_ENABLE to DP, DM;
see
TX_ENABLE to DP, DM;
see
TX_ENABLE to DP, DM;
see
DP, DM to DAT, SE0;
see
DP, DM to DAT, SE0;
see
0.3 V
HSF
t
t
PHZ
0.9 V
PLZ
10 %
, t
Figure 28
Figure 28
Figure 28
Figure 28
Figure 29
Figure 29
FF
, t
LF
amb
Rev. 01 — 28 May 2008
004aaa861
004aaa574
= 40 C to +85 C; unless otherwise specified.
Fig 27. Timing of DAT and SE0 when transmitting to
Fig 29. Timing of DAT and SE0 when receiving from
1.8 V
differential
data lines
V
V
0 V
logic input
OH
OL
logic output
Figure
0.8 V
2.0 V
V
V
differential
data lines
OH
…continued
OL
DP and DM
DP and DM
0.9 V
30. This timing applies to synchronous
ISP1507E; ISP1507F
V
CRS
Min
-
-
-
-
-
-
t
PLH(drv)
V
t
PLH(rcv)
CRS
0.9 V
ULPI HS USB OTG transceiver
Typ
-
-
-
-
-
-
Max
12
12
20
20
17
17
© NXP B.V. 2008. All rights reserved.
t
PHL(drv)
0.9 V
t
V
PHL(rcv)
CRS
V
004aaa985
004aaa573
CRS
Unit
ns
ns
ns
ns
ns
ns
0.9 V
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