ISP1507EBS,518 NXP Semiconductors, ISP1507EBS,518 Datasheet - Page 30

• Manufacturer Part Number: ISP1507EBS,518
• Description: RF Transceiver USB 2.0 ULPI TRNSCVR
• Manufacturer: NXP Semiconductors

Specifications of ISP1507EBS,518

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Power Supply Requirement: Single
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Compliant
• Other names: 935285498518 ISP1507EBS-T

NXP Semiconductors
ISP1507E_ISP1507F_1
Product data sheet
Fig 10. Example of register write, register read, extended register write and extended register read
DATA[3:0]
CLOCK
STP
NXT
DIR
AD indicates the address byte, and D indicates the data byte.
9.6 Register read and write operations
9.7 USB reset and high-speed detection handshake (chirp)
(REGW)
TXCMD
register write
immediate
enable HostDisconnect by setting the HOST_DISCON_R and HOST_DISCON_F bits in
the USB_INTR_EN_R_E and USB_INTR_EN_F_E registers, respectively. Changes in
HostDisconnect will cause the PHY to send an RXCMD to the link with the updated value.
Figure 10
addressing and extended addressing register operations. Extended register addressing is
optional for links. Note that register operations will be aborted if the ISP1507 unexpectedly
asserts DIR during the operation. When a register operation is aborted, the link must retry
until successful. For more information on register operations, refer to UTMI+ Low Pin
Interface (ULPI) Specification Rev. 1.1 .
Figure 11
handshake (chirp). The sequence is shown for hosts and peripherals.
show all RXCMD updates, and timing is not to scale. The sequence is as follows:
1. USB reset: The host detects a peripheral attachment as low-speed if DM is HIGH and
D
as full-speed if DP is HIGH. If a host detects a full-speed peripheral, it resets the
peripheral by writing to the Function Control register (see
XCVRSELECT[1:0] = 00b (high-speed) and TERMSELECT = 0b are then set which
drives SE0 on the bus (DP and DM are connected to ground through 45 ). The host
also sets OPMODE[1:0] = 10b for correct chirp transmit and receive. The start of SE0
is labeled T
Remark: To receive chirp signaling, the host must also consider the high-speed
differential receiver output. The host controller must interpret LINESTATE[1:0] as
shown in
shows the register read and write sequences. The ISP1507 supports immediate
shows the sequence of events for USB reset and high-speed detection
TXCMD
(EXTW) AD D
register write
extended
Table
0
.
12.
Rev. 01 — 28 May 2008
TXCMD
(REGR)
register read
immediate
D
ISP1507E; ISP1507F
TXCMD
(EXTW)
register read
extended
AD
ULPI HS USB OTG transceiver
D
Section
Figure 11
10.1.2).
© NXP B.V. 2008. All rights reserved.
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