ISP1507EBS,518 NXP Semiconductors, ISP1507EBS,518 Datasheet - Page 48

• Manufacturer Part Number: ISP1507EBS,518
• Description: RF Transceiver USB 2.0 ULPI TRNSCVR
• Manufacturer: NXP Semiconductors

Specifications of ISP1507EBS,518

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Power Supply Requirement: Single
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Compliant
• Other names: 935285498518 ISP1507EBS-T

NXP Semiconductors
Table 26.
Table 27.
ISP1507E_ISP1507F_1
Product data sheet
Bit
Symbol
Reset
Access
Bit
7
6
5
4
3
2
1
0
Symbol
INTF_PROT_DIS
IND_PASSTHRU
IND_COMPL
-
CLOCK_
SUSPENDM
-
3PIN_FSLS_
SERIAL
-
INTF_CTRL - Interface Control register (address R = 07h to 09h, W = 07h, S = 08h, C = 09h) bit allocation
INTF_CTRL - Interface Control register (address R = 07h to 09h, W = 07h, S = 08h, C = 09h) bit
description
PROT_DIS
10.1.4 OTG_CTRL register
R/W/S/C
INTF_
7
0
This register controls various OTG functions of the ISP1507. The bit allocation of the
OTG_CTRL register is given in
Description
Interface Protect Disable: Controls circuitry built into the ISP1507 to protect the ULPI when the
link 3-states STP and DATA[3:0]. When this bit is enabled, the ISP1507 will automatically detect
when the link stops driving STP.
0b — Enables the interface protect circuit (default). The ISP1507 attaches a weak pull-up
resistor on STP. If STP is unexpectedly HIGH, the ISP1507 attaches weak pull-down resistors
on DATA[3:0], protecting data inputs.
1b — Disables the interface protect circuit, detaches weak pull-down resistors on DATA[3:0],
and a weak pull-up resistor on STP.
Indicator Pass-through: The ISP1507 does not support the qualification of an external FAULT
with the internal V
or the V
logic 1.
0b — Not supported.
1b — The complement output signal is not qualified with the internal A_VBUS_VLD comparator.
The link must always set this bit to logic 1.
Indicator Complement: Informs the PHY to invert the FAULT input signal, generating the
complement output. For details, see
0b — The ISP1507 will not invert the FAULT signal (default).
1b — The ISP1507 will invert the FAULT signal.
reserved
Clock Suspend LOW: Active LOW clock suspend.
Powers down the internal clock circuitry only. By default, the clock will not be powered in 3-pin
serial mode.
Valid only in 3-pin serial mode. Valid only when SUSPENDM is set to logic 1, otherwise this bit
is ignored.
0b — Clock will not be powered in 3-pin serial mode (default).
1b — Clock will be powered in 3-pin serial mode.
reserved
3-Pin Full-Speed Low-Speed Serial Mode: Changes the ULPI to a 3-bit serial interface. The
PHY will automatically clear this bit when 3-pin serial mode is exited.
0b — Full-speed or low-speed packets are sent using the parallel interface (default).
1b — Full-speed or low-speed packets are sent using the 3-pin serial interface.
reserved
IND_PASS
R/W/S/C
THRU
6
0
BUS
power is connected to the V
R/W/S/C
COMPL
IND_
A_VBUS_VLD
5
0
Rev. 01 — 28 May 2008
reserved
R/W/S/C
comparator. Either a digital FAULT is input on the V
Table
4
0
Section
28.
BUS
SUSPENDM
CLOCK_
R/W/S/C
/FAULT pin, not both. This bit must always be set to
9.5.2.2.
3
0
ISP1507E; ISP1507F
reserved
R/W/S/C
ULPI HS USB OTG transceiver
2
0
3PIN_FSLS
_SERIAL
R/W/S/C
1
0
© NXP B.V. 2008. All rights reserved.
BUS
/FAULT pin
reserved
R/W/S/C
0
0
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