PIC24F04KA200T-I/ST Microchip Technology, PIC24F04KA200T-I/ST Datasheet - Page 98

• Manufacturer Part Number: PIC24F04KA200T-I/ST
• Description: PIC24F Core, 4KB Flash, 512B RAM, 3V, Deep Sleep, 10-bit 500ksps ADC, CTMU, UART
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24F04KA200T-I/ST

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 4KB (1.375K x 24)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC24F04KA201 FAMILY
REGISTER 9-2:
DS39937B-page 96
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-9
bit 8
bit 7
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
R/W-0, HS
DSFLT
U-0
—
2:
3:
All register bits are cleared when the DSCON<DSEN> bit is set.
All register bits are reset only in the case of a POR event outside Deep Sleep mode, except the DSPOR
bit, which does not reset on a POR event that is caused due to a Deep Sleep exit.
Unlike the other bits in this register, this bit can be set outside of Deep Sleep.
Unimplemented: Read as ‘0’
DSINT0: Interrupt-on-Change bit
1 = Interrupt-on-change was asserted during Deep Sleep
0 = Interrupt-on-change was not asserted during Deep Sleep
DSFLT: Deep Sleep Fault Detected bit
1 = A Fault occurred during Deep Sleep, and some Deep Sleep configuration settings may have been
0 = No Fault was detected during Deep Sleep
Unimplemented: Read as ‘0’
DSWDT: Deep Sleep Watchdog Timer Time-out bit
1 = The Deep Sleep Watchdog Timer timed out during Deep Sleep
0 = The Deep Sleep Watchdog Timer did not time out during Deep Sleep
Unimplemented: Read as ‘0’
DSMCLR: MCLR Event bit
1 = The MCLR pin was active and was asserted during Deep Sleep
0 = The MCLR pin was not active, or was active, but not asserted during Deep Sleep
Unimplemented: Read as ‘0’
DSPOR: Power-on Reset Event bit
1 = The V
0 = The V
U-0
U-0
corrupted
—
—
DSWSRC: DEEP SLEEP WAKE-UP SOURCE REGISTER
DD
DD
supply POR circuit was active and a POR event was detected
supply POR circuit was not active, or was active but did not detect a POR event
HS = Hardware Settable bit
W = Writable bit
‘1’ = Bit is set
U-0
U-0
—
—
R/W-0, HS
DSWDT
U-0
(2,3)
—
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
U-0
—
—
R/W-0, HS
DSMCLR
U-0
—
© 2009 Microchip Technology Inc.
(1)
x = Bit is unknown
U-0
U-0
—
—
DSPOR
R/W-0, HS
R/W-0, HS
DSINT0
(2,3)
bit 8
bit 0