PIC24F04KA200T-I/ST Microchip Technology, PIC24F04KA200T-I/ST Datasheet - Page 37

• Manufacturer Part Number: PIC24F04KA200T-I/ST
• Description: PIC24F Core, 4KB Flash, 512B RAM, 3V, Deep Sleep, 10-bit 500ksps ADC, CTMU, UART
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24F04KA200T-I/ST

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 4KB (1.375K x 24)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 4-17:
TABLE 4-18:
TABLE 4-19:
CMSTAT
CVRCON
CM1CON
CM2CON
Legend:
RCON
OSCCON
CLKDIV
OSCTUN
REFOCON
HLVDCON
Legend:
Note
DSWSRC
DSGPR0
DSGPR1
Legend:
Note
File Name
DSCON
File Name
Name
File
1:
2:
1:
Addr
0630
0632
0634
0636
Addr
0758
075A
075C
075E
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
RCON register Reset values are dependent on type of Reset.
OSCCON register Reset values are dependent on configuration fuses and by type of Reset.
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
The Deep Sleep registers are only reset on a V
Addr
074E
0740
0742
0744
0748
0756
CMSIDL
DUAL COMPARATOR REGISTER MAP
CLOCK CONTROL REGISTER MAP
DEEP SLEEP REGISTER MAP
Bit 15
Bit 15
DSEN
HLVDEN
CON
CON
TRAPR
ROEN
Bit 15
—
—
ROI
—
—
Bit 14
IOPUWR SBOREN
Bit 14
COE
COE
COSC2
DOZE2
—
—
Bit 14
—
—
—
—
—
Bit 13
CPOL
CPOL
Bit 13
ROSSLP
COSC1
HLSIDL
DOZE1
—
—
Bit 13
—
—
—
CLPWR
CLPWR
Bit 12
Bit 12
COSC0
DOZE0
ROSEL
—
—
—
—
Bit 12
—
—
—
DD
POR event.
Bit 11
Bit 11
RODIV3
DOZEN
—
—
—
—
—
—
Bit 11
—
—
—
—
Bit 10
Bit 10
RCDIV2
RODIV2
NOSC2
—
—
DPSLP
—
—
—
—
Bit 10
—
—
C2EVT
CEVT
CEVT
Bit 9
RCDIV1
RODIV1 RODIV0
Bit 9
NOSC1
Deep Sleep General Purpose Register 0
Deep Sleep General Purpose Register 1
—
—
—
Bit 9
—
—
—
DSINT0
RCDIV0
PMSLP
NOSC0
Bit 8
C1EVT
COUT
COUT
Bit 8
Bit 8
—
—
—
—
CLKLOCK
DSFLT
EVPOL1
EVPOL1
CVREN
Bit 7
EXTR
VDIR
Bit 7
—
Bit 7
—
—
—
—
EVPOL0
EVPOL0
Bit 6
CVROE
BGVST
—
—
Bit 6
SWR
Bit 6
—
—
—
—
—
SWDTEN
Bit 5
CVRR
IRVST
LOCK
TUN5
—
—
Bit 5
Bit 5
—
—
—
—
—
DSWDT
CVRSS
Bit 4
CREF
CREF
—
Bit 4
WDTO
TUN4
Bit 4
—
—
—
—
—
Bit 3
CVR3
HLVDL3
—
—
Bit 3
SLEEP
TUN3
—
—
—
Bit 3
CF
—
—
DSMCLR
Bit 2
CVR2
HLVDL2
—
Bit 2
TUN2
Bit 2
IDLE
—
—
—
—
—
—
DSBOR
Bit 1
SOSCEN OSWEN (Note 2)
C2OUT
HLVDL1
CVR1
CCH1
CCH1
—
Bit 1
TUN1
Bit 1
BOR
—
—
RELEASE
DSPOR
C1OUT
Bit 0
HLVDL0
CVR0
CCH0
CCH0
Bit 0
TUN0
Bit 0
POR
—
—
Resets
(Note 1)
Resets
Resets
0000
0000
0000
0000
0000
0000
0000
0000
3140
0000
0000
0000
All
All
All
(1)