PIC24F04KA200T-I/ST Microchip Technology, PIC24F04KA200T-I/ST Datasheet - Page 165

• Manufacturer Part Number: PIC24F04KA200T-I/ST
• Description: PIC24F Core, 4KB Flash, 512B RAM, 3V, Deep Sleep, 10-bit 500ksps ADC, CTMU, UART
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24F04KA200T-I/ST

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 4KB (1.375K x 24)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.0
PIC24F04KA201 family devices include several
features intended to maximize application flexibility and
reliability, and minimize cost through elimination of
external components. These are:
• Flexible Configuration
• Watchdog Timer (WDT)
• Code Protection
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit Emulation
REGISTER 23-1:
© 2009 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-2
bit 1
bit 0
Note:
U-0
—
SPECIAL FEATURES
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information on the
Watchdog
Integration and Programming Diagnostics,
refer to the individual sections of the
“PIC24F
provided below:
• Section 9. “Watchdog Timer (WDT)”
• Section 36. “High-Level Integration
• Section 33. “Programming and
(DS39697)
with Programmable High/Low-Voltage
Detect (HLVD)” (DS39725)
Diagnostics” (DS39716)
Unimplemented: Read as ‘0’
GSS0: General Segment Code Flash Code Protection bit
1 = No protection
0 = Standard security enabled
GWRP: General Segment Code Flash Write Protection bit
1 = General segment may be written
0 = General segment is write-protected
U-0
—
FGS: GENERAL SEGMENT CONFIGURATION REGISTER
Family
Timer,
C = Clearable bit
‘1’ = Bit is set
Reference
High-Level
U-0
—
Manual”
Device
U-0
—
Preliminary
PIC24F04KA201 FAMILY
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
23.1
The Configuration bits can be programmed (read as ‘0’),
or left unprogrammed (read as ‘1’), to select various
device configurations. These bits are mapped starting at
program memory location, F80000h. A complete list is
provided in Table 23-1. A detailed explanation of the
various bit functions is provided in Register 23-1 through
Register 23-7.
The address, F80000h, is beyond the user program
memory space. In fact, it belongs to the configuration
memory space (800000h-FFFFFFh), which can only be
accessed using table reads and table writes.
TABLE 23-1:
FGS
FOSCSEL
FOSC
FWDT
FPOR
FICD
FDS
U-0
—
Configuration
Register
Configuration Bits
U-0
—
CONFIGURATION REGISTERS
LOCATIONS
x = Bit is unknown
R/C-1
GSS0
Address
F8000C
F8000A
F8000E
F80004
F80006
F80008
F80010
DS39937B-page 163
GWRP
R/C-1
bit 0