PIC24F04KA200T-I/ST Microchip Technology, PIC24F04KA200T-I/ST Datasheet
PIC24F04KA200T-I/ST
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PIC24F04KA200T-I/ST Summary of contents
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... XLP™ Technology © 2009 Microchip Technology Inc. PIC24F04KA201 Family 14/20-Pin General Purpose, 16-Bit Flash Microcontrollers Preliminary Data Sheet DS39937B ...
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... PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Microchip Technology Inc. PIC24F04KA201 FAMILY Analog Features: • 10-Bit 9-Channel Analog-to-Digital Converter: - 500 ksps conversion rate - Conversion available during Sleep and Idle • Dual Analog Comparators with Programmable Input/ Output Configuration • Charge Time Measurement Unit (CTMU): - Used for capacitance sensing - Compatible with mTouch™ ...
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... All device pins have a maximum voltage of 3.6V and are not 5V tolerant. Note 1: DS39937B-page 2 14 /RA5 REFO/U1RX/SS1/T2CK/T3CK/INT0/CTPLS/CN11/RB15 AN10/CV /U1TX/SDI1/OCFA/C1OUT/INT1/CTED2/CN12/RB14 REF 5 10 OC1/IC1/C2OUT/INT2/CTED1/CN8/RA6 SDA1/U1BCLK/U1RTS/SDO1/CN21/RB9 6 9 SCL1/U1CTS/SCK1/CN22/RB8 8 7 /RA5 +/CN2/RA0 -/CN3/RA1 REFO/SS1/T2CK/T3CK/CN11/RB15 AN10/CV /SDI1/OCFA/C1OUT/INT1/CN12/RB14 17 REF 5 16 AN11/SDO1/CTPLS/CN13/RB13 AN12/HLVDIN/SCK1/CTED2/CN14/RB12 6 15 OC1/IC1/C2OUT/INT2/CTED1/CN8/RA6 7 14 SDA1/U1BCLK/U1RTS/CN21/RB9 8 13 SCL1/U1CTS/CN22/RB8 9 12 U1TX/INT0/CN23/RB7 10 11 Preliminary © 2009 Microchip Technology Inc. ...
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... Pin Diagrams (Continued) (1,2) 20-Pin QFN AN2/C2INB/CN4/RB0 AN3/C2INA/CN5/RB1 U1RX/U1BCLK/CN6/RB2 OSCI/CLKI/AN4/C1INB/CN30/RA2 OSCO/CLKO/AN5/C1INA/CN29/RA3 Connecting the bottom pad to Vss is recommended. Note 1: All device pins have a maximum voltage of 3.6V and are not 5V tolerant. 2: © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY REFO/SS1/T2CK/T3CK/CN11/RB15 15 1 AN10/CV /SDI1/OCFA/C1OUT/INT1/CN12/RB14 2 14 ...
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... Electrical Characteristics .......................................................................................................................................................... 185 27.0 Packaging Information.............................................................................................................................................................. 205 Appendix A: Revision History............................................................................................................................................................. 213 Index .................................................................................................................................................................................................. 215 The Microchip Web Site ..................................................................................................................................................................... 219 Customer Change Notification Service .............................................................................................................................................. 219 Customer Support .............................................................................................................................................................................. 219 Reader Response .............................................................................................................................................................................. 220 Product Identification System............................................................................................................................................................. 221 DS39937B-page 4 Preliminary © 2009 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY Preliminary DS39937B-page 5 ...
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... PIC24F04KA201 FAMILY NOTES: DS39937B-page 6 Preliminary © 2009 Microchip Technology Inc. ...
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... Hardware support for 32-bit by 16-bit division • An instruction set that supports multiple addressing modes and is optimized for high-level languages, such as C • Operational performance MIPS © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY 1.1.2 POWER-SAVING TECHNOLOGY The PIC24F04KA200 and PIC24F04KA201 devices incorporate a range of features that can significantly reduce power consumption during operation ...
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... Additional I/O on 20-Pin Devices ( I/O pins) • Data EEPROM memory • Boot Segment and General Segments for Program Code (with available code protection) • One Additional UART (2 total) Preliminary © 2009 Microchip Technology Inc. available on the family has the following ...
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... Input Change Notification Interrupt Serial Communications: UART SPI (3-wire/4-wire C™ 10-Bit Analog-to-Digital Module (input channels) Analog Comparators Resets (and delays) Instruction Set Packages © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY DC – 32 MHz 4K 1408 512 25 (21/4) PORTA<6:0> PORTB<15:14, 9:8, 4> PORTB<15:12, 9:7, 4, 2:0> 12 ...
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... EA MUX 24 16 Inst Latch Inst Register Divide Control Signals Support Reg Array 17x17 Multiplier 16-Bit ALU MCLR 10-Bit Timer2/3 CTMU Timer1 ADC (1) CN1-17 I2C1 OC1/PWM SPI1 Preliminary 16 PORTA (1) RA<6:0> (1) PORTB RB<15:12, 9:7> RB<4, 2:0> Comparators UART1 © 2009 Microchip Technology Inc. ...
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... CTED2 11 15 CTPLS 12 16 IC1 10 14 INT0 12 11 INT1 11 17 INT2 Schmitt Trigger input buffer, ANA = Analog level input/output, I Legend: © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY Input I/O 20-Pin Buffer QFN 19 I ANA 20 I ANA 1 I ANA 2 I ANA 4 I ANA ...
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... Slave Select Input/Frame Select Output (SPI1 Timer1 Clock Timer2 Clock Timer3 Clock UART1 Clear to Send Input 10 O — UART1 Request to Send Output UART1 Receive 8 O — UART1 Transmit Output 2 2 C™ C/SMBus input buffer Preliminary Description © 2009 Microchip Technology Inc. ...
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... REF REF Schmitt Trigger input buffer, ANA = Analog level input/output, I Legend: © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY Input I/O 20-Pin Buffer QFN 17 P — Positive Supply for Peripheral Digital Logic and I/O Pins 18 P — Programming Mode Entry Voltage ...
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... PIC24F04KA201 FAMILY NOTES: DS39937B-page 14 Preliminary © 2009 Microchip Technology Inc. ...
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... REF REF reference for analog modules is implemented The AV and AV pins must always be Note connected, regardless of whether any of the analog modules are being used. The minimum mandatory connections are shown in Figure 2-1. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY FIGURE 2- MCLR (2) C6 ...
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... Overstress (EOS). Ensure that the MCLR pin V IH Preliminary pin provides two specific device may be all that is required. The DD may be beneficial. A typical EXAMPLE OF MCLR PIN CONNECTIONS R1 R2 MCLR PIC24FXXXX JP C1 and V specifications are met and V specifications are met. IL © 2009 Microchip Technology Inc. ...
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... Frequency (MHz) Data for Murata GRM21BF50J106ZE01 shown. Note: Measurements at 25° bias. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY 2.5 ICSP Pins The PGECx and PGEDx pins are used for In-Circuit Serial Programming (ICSP) and debugging purposes recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible ...
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... Devices” 2.8 Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a 1 kΩ kΩ resistor to V output to logic low Preliminary on unused pins and drive the SS © 2009 Microchip Technology Inc. ...
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... Register Indirect modes. Each group offers up to seven addressing modes. Instructions are associated with predefined addressing modes depending upon their functional requirements. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY For most instructions, the core is capable of executing a data (or program data) memory read, a working ...
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... Description Working Register Array 23-Bit Program Counter ALU STATUS Register Stack Pointer Limit Value Register Table Memory Page Address Register Program Space Visibility Page Address Register Repeat Loop Counter Register CPU Control Register Preliminary Peripheral Modules © 2009 Microchip Technology Inc. ...
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... PROGRAMMER’S MODEL W0 (WREG) Divider Working Registers W1 W2 Multiplier Registers W10 W11 W12 W13 W14 W15 22 Registers or bits shadowed for PUSH.S and POP.S instructions. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY 15 0 Frame Pointer 0 Stack Pointer 0 SPLIM TBLPAG 7 0 PSVPAG 15 0 RCOUNT ...
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... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared th low-order bit (for byte-sized data low-order bit of the result has occurred (1,2) Preliminary U-0 U-0 R/W-0, HSC — — DC bit bit Bit is unknown th low-order bit (for word-sized data) © 2009 Microchip Technology Inc. ...
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... Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY U-0 U-0 U-0 — ...
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... All multi-bit shift instructions only support Register Direct Addressing for both the operand source and result destination. A full summary of instructions that use the shift operation is provided below in Table 3-2. Description Preliminary © 2009 Microchip Technology Inc. ...
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... TBLRD/TBLWT operations, which use TBLPAG<7> to permit access to the Configuration bits and Device ID sections of the configuration memory space. The memory map for the PIC24F04KA201 family of devices is displayed in Figure 4-1. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY FIGURE 4-1: PROGRAM SPACE MEMORY MAP FOR ...
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... FOSC FWDT FPOR FICD FDS least significant word Instruction Width Preliminary DEVICE CONFIGURATION WORDS FOR PIC24F04KA201 FAMILY DEVICES Configuration Word Addresses F80000 F80004 F80006 F80008 F8000A F8000C F8000E F80010 PC Address (lsw Address) 0 000000h 000002h 000004h 000006h © 2009 Microchip Technology Inc. ...
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... Data RAM 0DFFh 1FFF 7FFFh 8001h FFFFh Data memory areas are not shown to scale. Note: © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY 4.2.1 DATA SPACE WIDTH The data memory byte-addressable, 16-bit wide blocks. Data is aligned in data memory and registers as 16-bit words, but all the data space EAs resolve to bytes ...
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... System/DS/HLVD NVM/PMD Preliminary family devices, the entire xx80 xxA0 xxC0 xxE0 Interrupts — — — — — — I/O — — — — — — — — — — — — — — — — — © 2009 Microchip Technology Inc. ...
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TABLE 4-3: CPU CORE REGISTERS MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 ...
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TABLE 4-4: ICN REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name — (1) (1) CNEN1 0060 CN14IE CN13IE CN12IE CNEN2 0062 — CN30IE CN29IE — CNPU1 0068 — CN14PUE (1) CN13PUE (1) CN12PUE CN11PUE CNPU2 ...
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TABLE 4-6: TIMER REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON — ...
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TABLE 4-9: I C™ REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 I2C1RCV 0200 — — — — I2C1TRN 0202 — — — — I2C1BRG 0204 — — — — I2C1CON 0206 I2CEN — ...
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TABLE 4-12: PORTA REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name TRISA 02C0 — — — — PORTA 02C2 — — — — LATA 02C4 — — — — ODCA 02C6 — — — — ...
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TABLE 4-15: ADC REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ADC1BUFB 0316 ...
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TABLE 4-17: DUAL COMPARATOR REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name — — — CMSTAT 0630 CMSIDL CVRCON 0632 — — — — CM1CON 0634 CON COE CPOL CLPWR CM2CON 0636 CON COE CPOL ...
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TABLE 4-20: NVM REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 NVMCON 0760 WR WREN WRERR PGMONLY NVMKEY 0766 — — — — — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. ...
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... W15 (before CALL) PC<22:16> 000000000 <Free Word> W15 (after CALL) POP : [--W15] PUSH : [W15++] © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY 4.3 Interfacing Program and Data Memory Spaces The PIC24F architecture uses a 24-bit wide program space and 16-bit wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space ...
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... Bits Select 1 0 PSVPAG 8 Bits 23 Bits Preliminary <15> <14:1> <0> PC<22:1> 0 Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<15:0> xxxx xxxx xxxx xxxx (2) (1) Data EA<14:0> xxx xxxx xxxx xxxx 0 EA 1/0 16 Bits Bits Byte Select © 2009 Microchip Technology Inc. ...
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... D<7:0> of the data address, as above. Note that the data will always be ‘0’ when the upper ‘phantom’ byte is selected (byte select = 1). © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY In a similar fashion, two table instructions, TBLWTH and TBLWTL, are used to write individual bytes or words to a program space address. The details of their operation are explained in Section 5.0 “ ...
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... Execution in the first iteration • Execution in the last iteration • Execution prior to exiting the loop due to an interrupt • Execution upon re-entering the loop after an interrupt is serviced Preliminary Data EA<15:0> 1111’ or © 2009 Microchip Technology Inc. ...
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... When CORCON<2> and EA<15> Program Space PSVPAG The data in the page designated by PSVPAG is mapped into the upper half of the data memory space.... © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY Data Space 0 000000h 002BFEh PSV Area 800000h Preliminary 0000h Data EA<14:0> 8000h ...
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... PIC24F04KA201 FAMILY NOTES: DS39937B-page 42 Preliminary © 2009 Microchip Technology Inc. ...
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... Counter Using Table Instruction User/Configuration Space Select © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY Real-Time Streaming Protocol (RTSP) is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may write program memory data in blocks of 32 instructions (96 bytes time, and erase program memory in blocks of 32, 64 and 128 instructions (96,192 and 384 bytes time ...
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... Flash in RTSP mode. During a programming or erase operation, the processor stalls (waits) until the operation is finished. Setting the WR bit (NVMCON<15>) starts the operation and the WR bit is automatically cleared when the operation is finished. required for Preliminary © 2009 Microchip Technology Inc. ...
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... Erase entire general memory block programming operations All other combinations of NVMOP<5:0> are no operation. Note 1: Available in ICSP™ mode only. Refer to device programming specification. 2: The address in the Table Pointer decides which rows will be erased. 3: © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY R/W-0 U-0 U-0 PGMONLY — ...
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... Initialize PM Page Boundary SFR ; Initialize in-page EA[15:0] pointer ; Set base address of erase block ; Block all interrupts for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; Insert two NOPs after the erase ; command is asserted Preliminary © 2009 Microchip Technology Inc. ...
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... TBLPAG = __builtin_tblpage(&progAddr); offset = &progAddr & 0xFFFF; __builtin_tblwtl(offset, 0x0000); NVMCON = 0x4058; asm("DISI #5"); __builtin_write_NVM(); © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY // Initialize PM Page Boundary SFR // Initialize lower word of address // Set base address of erase block // with dummy latch write // Initialize NVMCON ...
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... Write PM low word into program latch ; Write PM high byte into program latch // Buffer of data to write // Initialize NVMCON // Initialize PM Page Boundary SFR // Initialize lower word of address // Write to address low word // Write to upper byte // Increment address Preliminary © 2009 Microchip Technology Inc. ...
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... MOV #0x55, W0 MOV W0, NVMKEY MOV #0xAA, W0 MOV W0, NVMKEY BSET NVMCON, #WR © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY ; Block all interrupts for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; 2 NOPs required after setting Wait for the sequence to be completed ...
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... PIC24F04KA201 FAMILY NOTES: DS39937B-page 50 Preliminary © 2009 Microchip Technology Inc. ...
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... SLEEP Uninitialized W Register © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. Most registers are unaffected by a Reset; their status is unknown on Power-on Reset (POR) and unchanged by all other Resets ...
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... R/C-0, HS — — DPSLP R/W-0, HS R/W-0, HS R/W-0, HS (2) WDTO SLEEP IDLE HS = Hardware Settable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) Preliminary U-0 R/W-0 — PMSLP bit 8 R/W-1, HS R/W-1, HS BOR POR bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Reset is chosen as shown in Table 6-2. If clock switching is disabled, the system clock source is always selected according to the oscillator Configuration bits. Refer to Section 8.0 “Oscillator Configuration” for further details. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY (1) (CONTINUED) Setting Event TABLE 6-2: OSCILLATOR SELECTION vs ...
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... T T POR PWRT FRC POR PWRT POR PWRT OST T PWRT T PWRT T PWRT T PWRT T T PWRT FRC T PWRT T T PWRT FRC — Preliminary © 2009 Microchip Technology Inc. Notes Delay — FRC LPRC LOCK LOCK OST LOCK — FRC LPRC LOCK LOCK ...
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... Even when the BOR is under software Note: control, the BOR Reset voltage level is still set by the BORV1:BORV0 Configuration bits. It can not be changed in software. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY 6.3.2 DETECTING BOR When BOR is enabled, the BOR bit (RCON<1>) is always reset to ‘1’ on any BOR or POR event. This makes it difficult to determine if a BOR event has occurred just by reading the state of BOR alone ...
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... Deep Sleep mode. Due to low-current consumption, accuracy may vary. The DSBOR trip point is around 2.0V. DSBOR is enabled by configuring FDS <DSLPBOR> DSLPBOR will re-arm the POR to ensure the device will reset if V drops below the POR threshold. DD Preliminary © 2009 Microchip Technology Inc. ...
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... Interrupt Vector 54 Interrupt Vector 116 Interrupt Vector 117 Note 1: See Table 7-2 for the interrupt vector list. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY vector. Each interrupt vector contains a 24-bit wide address. The value programmed into each interrupt vector location is the starting address of the associated Interrupt Service Routine (ISR) ...
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... IFS1<3> IEC1<3> IPC4<14:12> IFS4<8> IEC4<8> IPC17<2:0> IFS0<15> IEC0<15> IPC3<14:12> IFS0<2> IEC0<2> IPC0<10:8> IFS0<9> IEC0<9> IPC2<6:4> IFS0<10> IEC0<10> IPC2<10:8> IFS0<3> IEC0<3> IPC0<14:12> IFS0<7> IEC0<7> IPC1<14:12> IFS0<8> IEC0<8> IPC2<2:0> IFS4<1> IEC4<1> IPC16<6:4> IFS0<11> IEC0<11> IPC2<14:12> IFS0<12> IEC0<12> IPC3<2:0> © 2009 Microchip Technology Inc. ...
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... The IPCx registers are used to set the interrupt priority level for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY The INTTREG register contains the associated inter- rupt vector number and the new CPU interrupt priority level, which are latched into the Vector Number (VECNUM< ...
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... U-0 U-0 — — — R-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC (1) (1) ( Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2,3) Preliminary U-0 R-0, HSC (1) — DC bit 8 (1) ( bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... See Register 3-1 for the description of this bit, which is not dedicated to interrupt control functions. Note 1: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. 2: Bit 2 is described in Section 3.0 “CPU”. Note: © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY U-0 U-0 U-0 — ...
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... Unimplemented: Read as ‘0’ DS39937B-page 62 U-0 U-0 U-0 — — — R/W-0, HS R/W-0, HS R/W-0, HS MATHERR ADDRERR STKERR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0, HS U-0 OSCFAIL — bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY U-0 U-0 U-0 — — ...
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... Interrupt request has not occurred DS39937B-page 64 R/W-0, HS R/W-0, HS R/W-0, HS U1TXIF U1RXIF SPI1IF U-0 R/W-0, HS R/W-0, HS — T1IF OC1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0, HS R/W-0, HS SPF1IF T3IF bit 8 R/W-0, HS R/W-0, HS IC1IF INT0IF bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... MI2C1IF: Master I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY U-0 U-0 U-0 — — ...
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... Unimplemented: Read as ‘0’ DS39937B-page 66 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2009 Microchip Technology Inc. U-0 R/W-0, HS — HLVDIF bit 8 R/W-0, HS U-0 U1ERIF — bit Bit is unknown ...
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... IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE ...
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... Interrupt request has not occurred DS39937B-page 68 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 INT1IE CNIE CMIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 MI2C1IE SI2C1IE bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Interrupt request not enabled bit 7-2 Unimplemented: Read as ‘0’ bit 1 U1ERIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY U-0 U-0 U-0 — — — U-0 ...
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... Interrupt source is disabled DS39937B-page 70 R/W-0 U-0 R/W-1 T1IP0 — OC1IP2 R/W-0 U-0 R/W-1 IC1IP0 — INT0IP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC1IP1 OC1IP0 bit 8 R/W-0 R/W-0 INT0IP1 INT0IP0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... T2IP<2:0>: Timer2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY R/W-0 U-0 U-0 T2IP0 — — U-0 ...
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... Interrupt source is disabled DS39937B-page 72 R/W-0 U-0 R/W-1 U1RXIP0 — SPI1IP2 R/W-0 U-0 R/W-1 SPF1IP0 — T3IP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1IP1 SPI1IP0 bit 8 R/W-0 R/W-0 T3IP1 T3IP0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY R/W-0 U-0 U-0 NVMIP0 — — R/W-0 ...
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... Interrupt source is disabled DS39937B-page 74 R/W-0 U-0 R/W-1 CNIP0 — CMIP2 R/W-0 U-0 R/W-1 MI2C1P0 — SI2C1P2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 CMIP1 CMIP0 bit 8 R/W-0 R/W-0 SI2C1P1 SI2C1P0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY U-0 U-0 U-0 — — — U-0 ...
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... Unimplemented: Read as ‘0’ DS39937B-page 76 U-0 U-0 U-0 — — — R/W-0 U-0 U-0 INT2IP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... U1ERIP<2:0>: UART1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY U-0 U-0 U-0 — — — R/W-0 ...
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... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 HLVDIP1 HLVDIP0 bit Bit is unknown U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... VECNUM<6:0>: Vector Number of Pending Interrupt bits 0111111 = Interrupt Vector pending is number 135 • • • 0000001 = Interrupt Vector pending is number 9 0000000 = Interrupt Vector pending is number 8 © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY U-0 R-0 R-0 — ILR<3:0> R-0 R-0 R-0 VECNUM< ...
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... Only user interrupts with a priority level less can be disabled. Trap sources (level 8-15) cannot be disabled. The DISI instruction provides a convenient way to disable interrupts of priority levels 1-6 for a fixed period. Level 7 interrupt sources are not disabled by the DISI instruction. Preliminary © 2009 Microchip Technology Inc. ...
Page 83
... Secondary Oscillator SOSCO SOSCEN Enable SOSCI Oscillator © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY • Software-controllable switching between various clock sources. • Software-controllable postscaler for selective clocking of CPU for system power savings. • System frequency range declaration bits for EC mode ...
Page 84
... FCKSM<1:0> are both programmed (‘00’). Oscillator Source POSCMD<1:0> Internal 11 Internal 11 Internal 11 Secondary 00 Primary 10 Primary 00 Primary 10 Primary 01 Primary 00 Internal 11 Internal 11 Preliminary bit settings. The oscillator bits, POSCMD<1:0> FNOSC<2:0> Note 1, 2 111 1 110 1 101 1 100 011 011 010 010 010 1 001 1 000 © 2009 Microchip Technology Inc. ...
Page 85
... Reset values for these bits are determined by the FNOSC Configuration bits. Note 1: Also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected. 2: © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY The Clock Divider register (Register 8-2) controls the features associated with Doze mode, as well as the postscaler for the FRC oscillator ...
Page 86
... Initiate an oscillator switch to clock source specified by NOSC<2:0> bits 0 = Oscillator switch is complete Reset values for these bits are determined by the FNOSC Configuration bits. Note 1: Also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected. 2: DS39937B-page 84 (2) Preliminary © 2009 Microchip Technology Inc. ...
Page 87
... Unimplemented: Read as ‘0’ This bit is automatically cleared when the ROI bit is set and an interrupt occurs. Note 1: © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY R/W-1 R/W-0 R/W-0 (1) DOZE0 ...
Page 88
... U-0 U-0 — — R/W-0 R/W-0 (1) (1) (1) TUN4 TUN3 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 R/W-0 (1) (1) (1) TUN2 TUN1 TUN0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 89
... Perform the unlock sequence to allow a write to the OSCCON register low byte. 5. Set the OSWEN bit to initiate the oscillator switch. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY Once the basic sequence is completed, the system clock hardware responds automatically as follows: 1. The clock switching hardware compares the COSCx bits with the new value of the NOSCx bits ...
Page 90
... OSC1 and OSC2 will be powered down when the device enters Sleep mode. Clearing the ROSEL bit allows the reference output frequency to change as the system clock changes during any clock switches. Preliminary /2) available in OSC drive external devices in the © 2009 Microchip Technology Inc. ...
Page 91
... Base clock value divided by 2 0000 = Base clock value bit 7-0 Unimplemented: Read as ‘0’ The crystal oscillator must be enabled using the FOSC<2:0> bits; the crystal maintains the operation in Note 1: Sleep mode. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY R/W-0 R/W-0 R/W-0 ROSEL RODIV3 ...
Page 92
... PIC24F04KA201 FAMILY NOTES: DS39937B-page 90 Preliminary © 2009 Microchip Technology Inc. ...
Page 93
... BSET DSCON, #DSEN ; Enable Deep Sleep PWRSAV #SLEEP_MODE ; Put the device into Deep SLEEP mode © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY The assembly syntax of the PWRSAV instruction is shown in Example 9-1. SLEEP_MODE and IDLE_MODE are con- Note: stants defined in the assembler include file for the selected device ...
Page 94
... Deep Sleep mode. Exiting from Deep Sleep mode requires a change on the INT0 pin while in Deep Sleep mode. Preliminary © 2009 Microchip Technology Inc. CY for Sleep WDT” supply POR circuit, the ...
Page 95
... Deep Sleep mode. After exiting Deep Sleep, software can restore the data by reading the registers and clearing the RELEASE bit (DSCON<0>). © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY 9.2.4.4 I/O Pins During Deep Sleep ...
Page 96
... The DSEN bit is automatically cleared. 11. Read and clear the DPSLP status bit in RCON, and the DSWAKE status bits. 12. Read the DSGPRx registers (optional). 13. Once all state related configurations are complete, clear the RELEASE bit. 14. Application resumes normal operation. Preliminary ) PORs © 2009 Microchip Technology Inc. ...
Page 97
... All register bits are reset only in the case of a POR event outside of Deep Sleep mode. Note 1: Unlike all other events, a Deep Sleep BOR event will NOT cause a wake-up from Deep Sleep; this 2: re-arms POR. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY (1) U-0 U-0 U-0 — ...
Page 98
... U-0 U-0 U-0 — — — R/W-0, HS U-0 R/W-0, HS DSWDT — DSMCLR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2,3) Preliminary (1) U-0 R/W-0, HS — DSINT0 bit 8 U-0 R/W-0, HS (2,3) — DSPOR bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 99
... CPU Idles, waiting for something to invoke an interrupt routine. Enabling the automatic return to full-speed CPU operation on interrupts is enabled by set- ting the ROI bit (CLKDIV<15>). By default, interrupt events have no effect on Doze mode operation. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY 9.4 Selective Peripheral Module Control ...
Page 100
... PIC24F04KA201 FAMILY NOTES: DS39937B-page 98 Preliminary © 2009 Microchip Technology Inc. ...
Page 101
... CK WR PORT Data Latch Read LAT Read PORT © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin may be read, but the output driver for the parallel port bit will be disabled ...
Page 102
... Make sure that there is no external pull-up source/pull-down sink when the internal pull-ups/pull-downs are enabled. Pull-ups and pull-downs on change Note: notification disabled configured as a digital output. Preliminary , enable DD , enable pins should always be whenever the port pin is © 2009 Microchip Technology Inc. ...
Page 103
... SOSCO/ T1CK SOSCI TGATE 1 Set T1IF 0 Reset Equal © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY Figure 11-1 presents a block diagram of the 16-bit Timer1 module. To configure Timer1 for operation: 1. Set the TON bit (= 1). 2. Select the timer prescaler ratio using the TCKPS<1:0> bits. ...
Page 104
... DS39937B-page 102 U-0 U-0 — — R/W-0 U-0 R/W-0 TCKPS0 — TSYNC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared /2) Preliminary U-0 U-0 U-0 — — — bit 8 R/W-0 U-0 TCS — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 105
... Timer2 clock and gate inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the Timer3 interrupt flags. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY To configure Timer2/3 for 32-bit operation: 1. Set the T32 bit (T2CON<3> = 1). ...
Page 106
... The 32-Bit Timer Configuration (T32) bit must be set for 32-bit timer/counter operation. All control bits Note 1: are respective to the T2CON register. DS39937B-page 104 1x Gate Sync PR3 PR2 Comparator LSB TMR3 TMR2 TMR3HLD 16 Preliminary TCKPS<1:0> 2 TON Prescaler 1, 8, 64, 256 TGATE TCS Sync © 2009 Microchip Technology Inc. ...
Page 107
... TIMER2 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM T2CK TGATE 1 Set T2IF 0 Reset Equal FIGURE 12-3: TIMER3 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM T3CK TGATE 1 Set T3IF 0 Reset ADC Event Trigger Equal © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY 1x Gate Sync TMR2 Sync Comparator PR2 Sync ...
Page 108
... DS39937B-page 106 U-0 U-0 — — R/W-0 R/W-0 (1) TCKPS0 T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) /2) Preliminary U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 U-0 — TCS — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 109
... External clock from the T3CK pin (on the rising edge Internal clock (F OSC bit 0 Unimplemented: Read as ‘0’ When 32-bit operation is enabled (T2CON<3> = 1), these bits have no effect on Timer3 operation; all timer Note 1: functions are set through T2CON. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY U-0 U-0 (1) — — R/W-0 ...
Page 110
... PIC24F04KA201 FAMILY NOTES: DS39937B-page 108 Preliminary © 2009 Microchip Technology Inc. ...
Page 111
... Mode Select ICOV, ICBNE (IC1CON<4:3>) IC1CON System Bus © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY The PIC24F04KA201 family devices have one input capture channel. The input capture module has multiple operating modes, which are selected via the IC1CON register. The operating modes include: • ...
Page 112
... DS39937B-page 110 U-0 U-0 U-0 — — — R-0, HC R-0, HC R/W-0 ICOV ICBNE ICM2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 ICM1 ICM0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 113
... OC1IE bit. For further information on peripheral interrupts, refer to Section 7.0 “Interrupt Controller”. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY 10. To initiate another single pulse output, change the Timer and Compare register settings, if needed, and then issue a write to set the OCM bits to ‘ ...
Page 114
... Table 14-1 provides an example of PWM frequencies and resolutions for a device operating at 10 MIPS log 10 F • (Timer Prescale Value) PWM log ( /2, Doze mode and PLL are disabled. CY OSC Preliminary CALCULATING THE PWM (1) PERIOD • (Timer Prescale Value Doze mode CY OSC (1) ) bits © 2009 Microchip Technology Inc. ...
Page 115
... EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (F PWM Frequency 30.5 Hz Timer Prescaler Ratio 8 Period Register Value FFFFh Resolution (bits) 16 Based /2, Doze mode and PLL are disabled. Note 1: CY OSC © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY )/log 2) bits 10 2) bits 61 Hz 122 Hz 977 FFFFh 7FFFh 0FFFh ...
Page 116
... Each output compare channel can use one of two selectable time bases. Refer to the device data sheet for the 3: time bases associated with the module. DS39937B-page 114 Set Flag bit OC1IF Output Logic 3 OCM<2:0> Mode Select OCTSEL 0 1 Period Match Signals (3) (3) from Time Bases Preliminary ( (1) OC1 R Output Enable (2) OCFA © 2009 Microchip Technology Inc. ...
Page 117
... Initialize OC1 pin high, compare event forces OC1 pin low 001 = Initialize OC1 pin low, compare event forces OC1 pin high 000 = Output compare channel is disabled OCFA pin controls OC1 channel. Note 1: © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY U-0 U-0 U-0 — ...
Page 118
... U-0 — — — R/W-0 R/W-0 U-0 (2) (1) SMBUSDEL OC1TRIS — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) 2 C™)”. Preliminary U-0 U-0 — — bit 8 U-0 R/W-0 — — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 119
... SDO1 and SS1 are not used. Block diagrams of the module in Standard and Enhanced Buffer modes are displayed in Figure 15-1 and Figure 15-2. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY The devices of the PIC24F04KA201 family offer one SPI module on a device. ...
Page 120
... Control Clock SDO1 bit 0 SDI1 SPI1SR Transfer SPI1BUF Read SPI1BUF DS39937B-page 118 1:1 to 1:8 Secondary Prescaler Select Edge Shift Control Transfer Write SPI1BUF 16 Internal Data Bus Preliminary 1:1/4/16/64 Primary F CY Prescaler SPI1CON1<1:0> SPI1CON1<4:2> Enable Master Clock © 2009 Microchip Technology Inc. ...
Page 121
... SDO1 bit 0 SDI1 SPI1SR Transfer 8-Level FIFO Receive Buffer SPI1BUF Read SPI1BUF © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY To set up the SPI module for the Enhanced Buffer Slave mode of operation: 1. Clear the SPI1BUF register using interrupts: a) Clear the respective SPI1IF bit in the IFS0 register ...
Page 122
... R/W-0 SISEL2 SISEL1 SISEL0 HSC = Hardware Settable/Clearable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R-0, HSC R-0, HSC SPIBEC1 SPIBEC0 bit 8 R-0, HSC R-0, HSC SPITBF SPIRBF bit Clearable bit x = Bit is unknown © 2009 Microchip Technology Inc. ...
Page 123
... Automatically cleared in hardware when core reads SPI1BUF location, reading SPI1RXB. In Enhanced Buffer mode: Automatically set in hardware when SPI1 transfers data from SPI1SR to buffer, filling the last unread buffer location. Automatically cleared in hardware when a buffer location is available for a transfer from SPI1SR. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY Preliminary DS39937B-page 121 ...
Page 124
... DS39937B-page 122 R/W-0 R/W-0 R/W-0 DISSCK DISSDO MODE16 R/W-0 R/W-0 R/W-0 SPRE2 SPRE1 SPRE0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 (1) SMP CKE bit 8 R/W-0 R/W-0 PPRE1 PPRE0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 125
... Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 SPIBEN: Enhanced Buffer Enable bit 1 = Enhanced Buffer enabled 0 = Enhanced Buffer disabled (Legacy mode) © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY U-0 U-0 U-0 — — ...
Page 126
... Preliminary (1) 4:1 6:1 8:1 4000 2667 2000 1000 667 500 250 167 125 1250 833 625 313 208 156 © 2009 Microchip Technology Inc. ...
Page 127
... SCL1 and SDA1 during device configuration. Pin assignment is controlled by the I2C1SEL Configuration bit. Programming this bit (= 0) multiplexes the module to the SCL1 and SDA1 pins. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY 16.2 Communicating as a Master in a Single Master Environment The details of sending a message in Master mode depends on the communications protocol for the device being communicated with ...
Page 128
... Start and Stop Bit Generation Collision Detect Acknowledge Generation Clock Stretching I2C1TRN LSB Reload Control Preliminary Internal Data Bus Read Write I2C1MSK Read Write Read Write I2C1STAT Read Write I2C1CON Read Write Read Write I2C1BRG Read © 2009 Microchip Technology Inc. ...
Page 129
... Note 1: Address will be Acknowledged only if GCEN = 1. 2: Match on this address can only occur on the upper byte in 10-Bit Addressing mode. 3: © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY 16.4 Slave Address Masking The I2C1MSK register (Register 16-3) designates address bit positions as “don’t care” for both 7-Bit and 10-Bit Addressing modes ...
Page 130
... ACKEN RCEN PEN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2 C™ pins are controlled by port functions 2 C slave slave slave) Preliminary R/W-0 R/W-0 DISSLW SMEN bit 8 R/W-0, HC R/W-0, HC RSEN SEN bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 131
... Repeated Start condition not in progress bit 0 SEN: Start Condition Enable bit (when operating Initiates Start condition on SDA1 and SCL1 pins; hardware clear at end of master Start sequence 0 = Start condition not in progress © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY 2 C master; applicable during master receive) 2 ...
Page 132
... Bit is cleared nd byte of matched 10-bit address; hardware clear at Stop detection slave) Preliminary R-0, HSC R-0, HSC GCSTAT ADD10 bit 8 R-0, HSC R-0, HSC RBF TBF bit 0 HSC = Hardware Settable/Clearable bit x = Bit is unknown 2 C module is busy © 2009 Microchip Technology Inc. ...
Page 133
... Hardware set when I2C1RCV is written with received byte; hardware clear when software reads I2C1RCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2C1TRN is full 0 = Transmit complete, I2C1TRN is empty Hardware set when software writes to I2C1TRN; hardware clear at completion of data transmission. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY 2 C slave device address byte. ...
Page 134
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 R/W-0 R/W-0 — AMSK9 AMSK8 bit 8 R/W-0 R/W-0 AMSK1 AMSK0 bit Bit is unknown U-0 U-0 U-0 — — — bit 8 U-0 U-0 U-0 — — — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 135
... UART SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator IrDA Hardware Flow Control UART1 Receiver UART1 Transmitter © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY • Fully Integrated Baud Rate Generator (IBRG) with 16-Bit Prescaler • Baud Rates Ranging from 1 Mbps to 15 bps at 16 MIPS • ...
Page 136
... BRG timer to be reset (cleared). This ensures the BRG does not wait for a timer overflow before generating the new baud rate. Preliminary /(16 * 65536). UART BAUD RATE WITH (1) BRGH = • (U1BRG + – • Baud Rate = F /2, Doze mode CY OSC /4 CY (1) © 2009 Microchip Technology Inc. ...
Page 137
... Write ‘55h’ to U1TXREG – loads the Sync character into the transmit FIFO. 5. After the Break has been sent, the UTXBRK bit is reset by hardware. The Sync character now transmits. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY 17.5 Receiving in 8-Bit or 9-Bit Data Mode 1. ...
Page 138
... IREN RTSMD — R/W-0 R/W-0 R/W-0 RXINV BRGH PDSEL1 HC = Hardware Clearable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) Preliminary (2) (2) R/W-0 R/W-0 UEN1 UEN0 bit 8 R/W-0 R/W-0 PDSEL0 STSEL bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 139
... STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit This feature is only available for the 16x BRG mode (BRGH = 0). Note 1: Bit availability depends on pin availability. 2: © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY Preliminary DS39937B-page 137 ...
Page 140
... R-0, HSC RIDLE PERR FERR HC = Hardware Clearable bit HSC = Hardware Settable/Clearable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R-0, HSC R-1, HSC UTXBF TRMT bit 8 R/C-0, HS R-0, HSC OERR URXDA bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 141
... Receive buffer has not overflowed (clearing a previously set OERR bit (1 → 0 transition) will reset the receiver buffer and the RSR to the empty state) bit 0 URXDA: Receive Buffer Data Available bit (read-only Receive buffer has data; at least one more character can be read 0 = Receive buffer is empty © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY Preliminary DS39937B-page 139 ...
Page 142
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-x W-x — UTX8 bit 8 W-x W-x UTX1 UTX0 bit Bit is unknown U-0 R-0, HSC — URX8 bit 8 R-0, HSC R-0, HSC URX1 URX0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 143
... Trip Point V DD HLVDIN HLVDEN © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY An interrupt flag is set if the device experiences an excursion past the trip point in the direction of change. If the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to the interrupt ...
Page 144
... DS39937B-page 142 U-0 U-0 U-0 — — — U-0 R/W-0 R/W-0 — HLVDL3 HLVDL2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2009 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0 R/W-0 HLVDL1 HLVDL0 bit Bit is unknown ...
Page 145
... V REF voltage reference inputs may be shared with other analog input pins. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY A block diagram of the A/D Converter is displayed in Figure 19-1. To perform an A/D conversion: 1. ...
Page 146
... S/H DAC V INL 10-Bit SAR Data Formatting ADC1BUF0: ADC1BUFF AD1CON1 AD1CON2 AD1CON3 AD1CHS INH AD1PCFG AD1CSSL INL Sample Control Control Logic Input MUX Control Pin Config Control Preliminary Internal Data Bus 16 Comparator + Conversion Logic Conversion Control © 2009 Microchip Technology Inc. ...
Page 147
... A/D conversion is done 0 = A/D conversion is not done Values of ADC1BUFn registers will not retain their values once the ADON bit is cleared. Read out the Note 1: conversion values from the buffer before disabling the module. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY U-0 U-0 U-0 — ...
Page 148
... REF AV External V DD External V + pin External V REF (1) th sample/convert sequence th sample/convert sequence nd sample/convert sequence . This sets the inputs of the A Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 BUFM ALTS bit Bit is unknown - pin REF - pin REF SS © 2009 Microchip Technology Inc. ...
Page 149
... Unimplemented: Read as ‘0’ bit 5-0 ADCS<5:0>: A/D Conversion Clock Select bits 111111 = 32 • · · · 000001 = T CY 000000 = © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY R/W-0 R/W-0 R/W-0 SAMC4 SAMC3 SAMC2 R/W-0 R/W-0 R/W-0 ADCS4 ADCS3 ADCS2 U = Unimplemented bit, read as ‘ ...
Page 150
... U-0 R/W-0 R/W-0 — CH0SB3 CH0SB2 R/W-0 R/W-0 R/W-0 CH0SA4 CH0SA3 CH0SA2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared - Preliminary R/W-0 R/W-0 CH0SB1 CH0SB0 bit 8 R/W-0 R/W-0 CH0SA1 CH0SA0 bit Bit is unknown /2) BG /2) BG © 2009 Microchip Technology Inc. ...
Page 151
... Analog channel omitted from input scan bit 9-6 Unimplemented: Read as ‘0’ bit 5-0 CSSL<5:0>: A/D Input Pin Scan Selection bits 1 = Corresponding analog channel selected for input scan 0 = Analog channel omitted from input scan © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY R/W-0 R/W-0 R/W-0 PCFG12 PCFG11 ...
Page 152
... Threshold Voltage Leakage Current at the pin due to LEAKAGE various junctions R = Interconnect Resistance Sampling Switch Resistance Sample/Hold Capacitance (from DAC) HOLD Preliminary ≤ 5 kΩ (Typical HOLD = DAC capacitance = 4.4 pF (Typical negligible if Rs ≤ 5 kΩ. PIN © 2009 Microchip Technology Inc. ...
Page 153
... Voltage Level © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY Preliminary DS39937B-page 151 ...
Page 154
... PIC24F04KA201 FAMILY NOTES: DS39937B-page 152 Preliminary © 2009 Microchip Technology Inc. ...
Page 155
... BG C INA X CV REF © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY The comparator outputs may be directly connected to the CxOUT pins. When the respective COE equals ‘1’, the I/O pad logic makes the unsynchronized output of the comparator available on the pin. A simplified block diagram of the module is displayed in Figure 20-1 ...
Page 156
... IN Off (Read as ‘0’) CxOUT Comparator V > CxINA Compare BG CON = 1 , CREF = 0 COE INA X CxOUT Pin Comparator V > CON = 1 , CREF = 1 COE REF CxOUT Pin Preliminary Pin , CCH<1:0> COE - - Cx + CxOUT Pin Compare REF , CCH<1:0> COE - - Cx + CxOUT Pin © 2009 Microchip Technology Inc. ...
Page 157
... Non-inverting input connects to CxINA pin bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 CCH<1:0>: Comparator Channel Select bits 11 = Inverting input of comparator connects Inverting input of comparator connects to CxINB pin © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY R/W-0 U-0 U-0 CLPWR — — ...
Page 158
... U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2009 Microchip Technology Inc. R-0, HSC R-0, HSC C2EVT C1EVT bit 8 R-0, HSC R-0, HSC C2OUT C1OUT bit Bit is unknown ...
Page 159
... REF AV DD CVRSS = 0 CVREN CVRR V - REF © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY 21.1 Configuring the Comparator Voltage Reference The comparator voltage reference module is controlled through the CVRCON register (Register 21-1). The comparator voltage reference provides two ranges of comprehensive output voltage, each with 16 distinct levels. The range to be used is selected by the CVRR bit (CVRCON< ...
Page 160
... DD SS Value Selection 0 ≤ CVR<3:0> ≤ 15 bits REF ) RSRC ) RSRC )) + V - RSRC REF ) + (CVR<3:0>/32 RSRC REF Preliminary U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 R/W-0 CVR2 CVR1 CVR0 bit Bit is unknown /24 step size /32 step size - © 2009 Microchip Technology Inc. ...
Page 161
... CTMUICON register selects the current range of current source and trims the current. FIGURE 22-1: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR CAPACITANCE MEASUREMENT C APP © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY 22.1 Measuring Capacitance The CTMU generating an output pulse with a width equal to the time between edge events on two separate input channels ...
Page 162
... EDG1 Current Source EDG2 Output Pulse A/D Converter ANx PIC24F Device CTMU EDG1 Current Source Comparator - C2 CV REF Preliminary ) is connected to DELAY , is connected to C2INA. REF when an edge event DELAY charges above the CV DELAY REF and DELAY CTPLS © 2009 Microchip Technology Inc. ...
Page 163
... EDG2SEL<1:0>: Edge 2 Source Select bits 11 = CTED1 pin 10 = CTED2 pin 01 = OC1 module 00 = Timer1 module bit 4 EDG1POL: Edge 1 Polarity Select bit 1 = Edge 1 programmed for a positive edge response 0 = Edge 1 programmed for a negative edge response © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY R/W-0 R/W-0 R/W-0 TGEN EDGEN EDGSEQEN R/W-0 ...
Page 164
... DS39937B-page 162 R/W-0 R/W-0 R/W-0 ITRIM2 ITRIM1 ITRIM0 U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 IRNG1 IRNG0 bit 8 U-0 U-0 — — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 165
... Standard security enabled bit 0 GWRP: General Segment Code Flash Write Protection bit 1 = General segment may be written 0 = General segment is write-protected © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY 23.1 Configuration Bits The Configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’), to select various device configurations ...
Page 166
... Low-Power FRC oscillator with divide-by-N (LPFRCDIV) 111 = 8 MHz FRC oscillator with divide-by-N (FRCDIV) DS39937B-page 164 U-0 U-0 R/P-1 — — FNOSC2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2009 Microchip Technology Inc. R/P-1 R/P-1 FNOSC1 FNOSC0 bit Bit is unknown ...
Page 167
... CLKO output disabled bit 1-0 POSCMD<1:0>: Primary Oscillator Configuration bits 11 = Primary oscillator disabled Oscillator mode selected Oscillator mode selected 00 = External Clock mode selected © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY R/P-1 R/P-1 R/P Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
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... DS39937B-page 166 R/P-1 R/P-1 R/P-1 FWPSA WDTPS3 WDTPS2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/P-1 R/P-1 WDTPS1 WDTPS0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 1-0 FICD<1:0:> ICD Pin Select bits 10 = PGC2/PGD2 are used for programming the device 01 = PGC3/PGD3 are used for programming the device 00 Reserved; do not use © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY U-0 R/P-1 (2) — PWRTEN U = Unimplemented bit, read as ‘ ...
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... DS39937B-page 168 U-0 R/P-1 R/P-1 — DSWDTPS3 DSWDTPS2 DSWDTPS1 DSWDTPS0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2009 Microchip Technology Inc. R/P-1 R/P-1 bit Bit is unknown ...
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... Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 23-4 Unimplemented: Read as ‘0’ bit 3-0 REV<3:0>: Minor Revision Identifier bits © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY U-0 U-0 U-0 — — — FAMID4 ...
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... WDT option allows the user to enable the WDT for critical code segments and disable the WDT during non-critical segments for maximum power savings. LPRC Control WDTPS<3:0> WDT Postscaler Counter 1:1 to 1:32.768 1 ms/4 ms Preliminary Wake from Sleep WDT Overflow Reset © 2009 Microchip Technology Inc. ...
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... Configuration bit, GSS0. This bit inhibits external reads and writes to the program memory space; this has no direct effect in normal execution mode. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY Write protection is controlled by the GWRP bit for the general segment in the Configuration Word. When this bit is programmed to ‘ ...
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... PIC24F04KA201 FAMILY NOTES: DS39937B-page 172 Preliminary © 2009 Microchip Technology Inc. ...
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... PICSTART Plus Development Programmer - MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY 24.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...
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... MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. Preliminary ® DSCs on an instruction © 2009 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC24F04KA201 FAMILY 24.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD ...
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... IrDA , PowerSmart battery management, SEEVAL evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. Preliminary © 2009 Microchip Technology Inc. ® L security ICs, CAN ® ...
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... The bit in the W register or file register (specified by a literal value or indirectly by the contents of register ‘Wb’) © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY The literal instructions that involve data movement may use some of the following operands: • ...
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... One of 16 source working registers ∈ {W0..W15} Wns WREG W0 (working register used in file register instructions) Source W register ∈ { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws Source W register ∈ { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] } Wso DS39937B-page 178 Description Preliminary © 2009 Microchip Technology Inc. ...
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... Ws,#bit4 BSW BSW.C Ws,Wb BSW.Z Ws,Wb BTG BTG f,#bit4 BTG Ws,#bit4 BTSC BTSC f,#bit4 BTSC Ws,#bit4 © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY Description WREG WREG = f + WREG Wd = lit10 + lit5 WREG + (C) WREG = f + WREG + ( lit10 + lit5 + ( .AND. WREG WREG = f .AND. WREG Wd = lit10 .AND ...
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... Signed 32/16-bit Integer Divide Unsigned 16/16-bit Integer Divide Unsigned 32/16-bit Integer Divide Swap Wns with Wnd Find First One from Left (MSb) Side Find First One from Right (LSb) Side Preliminary © 2009 Microchip Technology Inc Status Flags Words Cycles Affected ...
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... POP POP f POP Wdo POP.D Wnd POP.S PUSH PUSH f PUSH Wso PUSH.D Wns PUSH.S © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY Description Go to Address Go to Indirect WREG = WREG = .IOR. WREG WREG = f .IOR. WREG Wd = lit10 .IOR .IOR .IOR. lit5 Link Frame Pointer ...
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... WREG – f WREG = WREG – – lit5 – WREG – f – (C) WREG = WREG – f – ( – Wb – ( lit5 – Wb – ( Nibble Swap Byte Swap Wn Read Prog<23:16> to Wd<7:0> Preliminary © 2009 Microchip Technology Inc Status Flags Words Cycles Affected 1 1 WDTO, Sleep 1 2 ...
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... XOR f XOR f,WREG XOR #lit10,Wn XOR Wb,Ws,Wd XOR Wb,#lit5, Ws,Wnd © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY Description Read Prog<15:0> Write Ws<7:0> to Prog<23:16> Write Ws to Prog<15:0> Unlink Frame Pointer .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR .XOR .XOR. lit5 Wnd = Zero-Extend Ws ...
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... PIC24F04KA201 FAMILY NOTES: DS39937B-page 184 Preliminary © 2009 Microchip Technology Inc. ...
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... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY ........................................... -0. ...
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... MHz – 1. MHz. DD Min Typ Max Unit -40 — +125 °C -40 — +85 ° INT – T )/θ Typ Max Unit Notes — °C — °C/W 1 108 — °C — °C — °C/W 1 — °C — °C — °C/W 1 © 2009 Microchip Technology Inc. ...
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... Operating temperature -40°C ≤ T ≤ +85°C for industrial A Param Symbol Characteristic No. DC18 V HLVD Voltage on V HLVD Transition © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) -40°C ≤ T Operating temperature (1) Min Typ Max Units 1.8 — 3 ...
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... Preliminary Conditions Valid for LPBOR and DSBOR ) Conditions 1.8V 0.5 MIPS MHz OSC 3.3V 1.8V 1 MIPS MHz OSC 3.3V 16 MIPS, 3. MHz OSC 2.5V FRC (4 MIPS MHz OSC 3.3V © 2009 Microchip Technology Inc. ...
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... MCLR – • WDT FSCM disabled • SRAM, program and data memory active • All PMD bits set except for modules being measured © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY DD Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) -40°C ≤ T ...
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... Preliminary Conditions 1.8V 1 MIPS MHz OSC 3.3V 16 MIPS, 3. MHz OSC 1.8V FRC (4 MIPS MHz OSC 3.3V 1.8V LPRC (31 kHz) 3.3V © 2009 Microchip Technology Inc. ...
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... The Δ current is the additional current consumed when the module is enabled. This current should be added to 3: the base I current. PD Current applies to Sleep only. 4: Current applies to Deep Sleep only. 5: © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial Operating temperature A Units (2) -40° ...
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... Preliminary ) (CONTINUED) PD Conditions Timer1 w/32 kHz Crystal: T132 (3) (SOSC – LP) (3,4) HLVD (3,4) BOR © 2009 Microchip Technology Inc. ...
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... The Δ current is the additional current consumed when the module is enabled. This current should be added to 3: the base I current. PD Current applies to Sleep only. 4: Current applies to Deep Sleep only. 5: © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial Operating temperature A Units (2) -40° ...
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... Preliminary Conditions SMBus disabled SMBus enabled 2.5V ≤ V ≤ V PIN 3.3V PIN SS ≤ V ≤ PIN DD Pin at high-impedance ≤ V ≤ PIN DD Pin at high-impedance ≤ V ≤ PIN DD ≤ V ≤ PIN DD XT and HS modes © 2009 Microchip Technology Inc. ...
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... Supply Current During DDP Programming Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Note 1: Self-write and block erase. 2: © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial Operating temperature A ...
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... DD Min Typ Max — — 10 Preliminary Units Comments — dB Units Comments /32 LSb – 1.5 LSb Ω — Conditions CTMUICON<1:0> CTMUICON<1:0> CTMUICON<1:0> Units Comments ns μs 10 Units Comments μs © 2009 Microchip Technology Inc. ...
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... SCLx, SDAx B Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only Note 1: and are not tested. © 2009 Microchip Technology Inc. PIC24F04KA201 FAMILY -40°C ≤ T ≤ +85°C for Industrial A range as described in Section 26.1 “DC Characteristics”. ...
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... All specified values are ). CY Preliminary OS31 OS31 ≤ +85°C for Industrial A Units Conditions MHz EC MHz ECPLL MHz XT MHz HS MHz HSPLL kHz SOSC — See parameter OS10 for F OSC value © 2009 Microchip Technology Inc. ...