PIC24F04KA200T-I/ST Microchip Technology, PIC24F04KA200T-I/ST Datasheet - Page 140

• Manufacturer Part Number: PIC24F04KA200T-I/ST
• Description: PIC24F Core, 4KB Flash, 512B RAM, 3V, Deep Sleep, 10-bit 500ksps ADC, CTMU, UART
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24F04KA200T-I/ST

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 4KB (1.375K x 24)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC24F04KA201 FAMILY
REGISTER 17-2:
DS39937B-page 138
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15,13
bit 14
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7-6
URXISEL1
UTXISEL1
R/W-0
R/W-0
UTXISEL<1:0>: Transmission Interrupt Mode Selection bits
11 = Reserved; do not use
10 = Interrupt when a character is transferred to the Transmit Shift Register (TSR), and as a result,
01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit operations
00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at
UTXINV: IrDA
If IREN = 0:
1 = U1TX Idle ‘0’
0 = U1TX Idle ‘1’
If IREN = 1:
1 = U1TX Idle ‘1’
0 = U1TX Idle ‘0’
Unimplemented: Read as ‘0’
UTXBRK: Transmit Break bit
1 = Send Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;
0 = Sync Break transmission disabled or completed
UTXEN: Transmit Enable bit
1 = Transmit enabled, U1TX pin controlled by UART1
0 = Transmit disabled, any pending transmission is aborted and buffer is reset. U1TX pin controlled by
UTXBF: Transmit Buffer Full Status bit (read-only)
1 = Transmit buffer is full
0 = Transmit buffer is not full, at least one more character can be written
TRMT: Transmit Shift Register Empty bit (read-only)
1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0 = Transmit Shift Register is not empty, a transmission is in progress or queued
URXISEL<1:0>: Receive Interrupt Mode Selection bits
11 = Interrupt is set on RSR transfer, making the receive buffer full (i.e., has 4 data characters)
10 = Interrupt is set on RSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters)
0x = Interrupt is set when any character is received and transferred from the RSR to the receive buffer.
URXISEL0
UTXINV
R/W-0
R/W-0
cleared by hardware upon completion
the PORT register.
the transmit buffer becomes empty
are completed
least one character open in the transmit buffer)
Receive buffer has one or more characters.
U1STA: UART1 STATUS AND CONTROL REGISTER
®
C = Clearable bit
HS = Hardware Settable bit
W = Writable bit
‘1’ = Bit is set
Encoder Transmit Polarity Inversion bit
UTXISEL0
ADDEN
R/W-0
R/W-0
R-1, HSC
RIDLE
U-0
—
Preliminary
HC = Hardware Clearable bit
HSC = Hardware Settable/Clearable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0, HC
R-0, HSC
UTXBRK
PERR
R-0, HSC
UTXEN
R/W-0
FERR
© 2009 Microchip Technology Inc.
x = Bit is unknown
R/C-0, HS
R-0, HSC
UTXBF
OERR
R-1, HSC
R-0, HSC
URXDA
TRMT
bit 8
bit 0