PIC24F04KA200T-I/ST Microchip Technology, PIC24F04KA200T-I/ST Datasheet - Page 121

• Manufacturer Part Number: PIC24F04KA200T-I/ST
• Description: PIC24F Core, 4KB Flash, 512B RAM, 3V, Deep Sleep, 10-bit 500ksps ADC, CTMU, UART
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24F04KA200T-I/ST

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 4KB (1.375K x 24)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

To set up the SPI module for the Enhanced Buffer
Master (EBM) mode of operation:
1.
2.
3.
4.
5.
6.
FIGURE 15-2:
© 2009 Microchip Technology Inc.
SS1/FSYNC1
If using interrupts:
a)
b)
c)
Write the desired settings to the SPI1CON1
and SPI1CON2 registers with the MSTEN bit
(SPI1CON1<5>) = 1.
Clear the SPIROV bit (SPI1STAT<6>).
Select Enhanced Buffer mode by setting the
SPIBEN bit (SPI1CON2<0>).
Enable SPI operation by setting the SPIEN bit
(SPI1STAT<15>).
Write the data to be transmitted to the SPI1BUF
register. Transmission (and reception) will start
as soon as data is written to the SPI1BUF
register.
SDO1
SCK1
SDI1
Clear the respective SPI1IF bit in the IFS0
register.
Set the respective SPI1IE bit in the IEC0
register.
Write the respective SPI1IPx bits in the
IPC2 register.
Read SPI1BUF
Control
Transfer
Sync
SPI1 MODULE BLOCK DIAGRAM (ENHANCED BUFFER MODE)
Receive Buffer
8-Level FIFO
bit 0
Control
SPI1SR
Clock
SPI1BUF
Shift Control
Transmit Buffer
8-Level FIFO
Preliminary
Transfer
Write SPI1BUF
PIC24F04KA201 FAMILY
Select
Edge
To set up the SPI module for the Enhanced Buffer
Slave mode of operation:
1.
2.
3.
4.
5.
6.
7.
8.
16
Clear the SPI1BUF register.
If using interrupts:
a)
b)
c)
Write the desired settings to the SPI1CON1 and
SPI1CON2 registers with the MSTEN bit
(SPI1CON1<5>) = 0.
Clear the SMP bit.
If the CKE bit is set, then the SSEN bit must be
set, thus enabling the SS1 pin.
Clear the SPIROV bit (SPI1STAT<6>).
Select Enhanced Buffer mode by setting the
SPIBEN bit (SPI1CON2<0>).
Enable SPI operation by setting the SPIEN bit
(SPI1STAT<15>).
Secondary
1:1 to 1:8
Prescaler
Clear the respective SPI1IF bit in the IFS0
register.
Set the respective SPI1IE bit in the IEC0
register.
Write the respective SPI1IPx bits in the
IPC2 register to set the interrupt priority.
Internal Data Bus
1:1/4/16/64
Prescaler
Primary
DS39937B-page 119
SPI1CON1<1:0>
SPI1CON1<4:2>
Enable
Master Clock
F
CY