PIC18F46K80T-I/ML Microchip Technology, PIC18F46K80T-I/ML Datasheet - Page 373
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PIC18F46K80T-I/ML
Manufacturer Part Number
PIC18F46K80T-I/ML
Description
ECAN, 64KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 44 QFN 8x8x0.9mm T/R
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K80-ISO.pdf
(628 pages)
Specifications of PIC18F46K80T-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
PIC18F46K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
35
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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23.4
The ADCON2 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set.
When the GO/DONE bit is set, sampling is stopped and
a conversion begins. The user is responsible for ensur-
ing the required acquisition time has passed between
selecting the desired input channel and setting the
GO/DONE bit.
This
(ADCON2<5:3>) remain in their Reset state (‘ 000 ’),
which is compatible with devices that do not offer
programmable acquisition times.
If desired, the ACQTx bits can be set to select a pro-
grammable acquisition time for the A/D module. When
the GO/DONE bit is set, the A/D module continues to
sample the input for the selected acquisition time, then
automatically begins a conversion. Since the acquisi-
tion time is programmed, there may be no need to wait
for an acquisition time between selecting a channel and
setting the GO/DONE bit.
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. If an acquisition time is programmed, there is
nothing to indicate if the acquisition time has ended or
if the conversion has begun.
23.5
The A/D conversion time per bit is defined as T
A/D conversion requires 14 T
The source of the A/D conversion clock is software
selectable.
The possible options for T
• 2 T
• 4 T
• 8 T
• 16 T
• 32 T
• 64 T
• Using the internal RC Oscillator
For correct A/D conversions, the A/D conversion clock
(T
minimum
Parameter 130 in
Table 23-1
the device operating frequencies and the A/D clock
source selected.
2011 Microchip Technology Inc.
AD
) must be as short as possible but greater than the
OSC
OSC
OSC
OSC
OSC
OSC
occurs
Selecting and Configuring
Automatic Acquisition Time
Selecting the A/D Conversion
Clock
shows the resultant T
T
AD
.
Table
when
(For
31-26.)
AD
more
the
are:
AD
per 12-bit conversion.
AD
ACQT<2:0>
times derived from
information,
AD
. The
see
Preliminary
bits
PIC18F66K80 FAMILY
TABLE 23-1:
23.6
The ANCON0, ANCON1, TRISA, TRISB, TRISC and
TRISC registers control the operation of the A/D port
pins. The port pins needed as analog inputs must have
their corresponding TRISx bits set (input). If the TRISx
bit is cleared (output), the digital output level (V
V
The A/D operation is independent of the state of the
CHS<3:0> bits and the TRISx bits.
Note 1:
OL
Note 1: When reading the PORT register, all pins
Operation
) will be converted.
16 T
32 T
64 T
2 T
4 T
8 T
AD Clock Source (T
RC
2:
OSC
OSC
OSC
Configuring Analog Port Pins
OSC
OSC
OSC
2: Analog levels on any pin defined as a
(2)
The RC source has a typical T
4 s.
For device frequencies above 1 MHz, the
device must be in Sleep mode for the
entire conversion or the A/D accuracy may
be out of specification.
configured as analog input channels will
read as cleared (a low level). Pins config-
ured as digital inputs will convert an
analog input. Analog levels on a digitally
configured
converted.
digital input may cause the digital input
buffer to consume current out of the
device’s specification limits.
T
FREQUENCIES
AD
ADCS<2:0>
vs. DEVICE OPERATING
000
100
001
101
010
110
x11
input
AD
)
will
DS39977C-page 373
be
Frequency
10.00 MHz
20.00 MHz
40.00 MHz
64.00 MHz
Maximum
1.00 MHz
2.50 MHz
5.00 MHz
Device
AD
accurately
time of
OH
(1)
or
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