PIC18F46K80T-I/ML Microchip Technology, PIC18F46K80T-I/ML Datasheet - Page 295
![ECAN, 64KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 44 QFN 8x8x0.9mm T/R](/photos/39/70/397090/qfn-44_sml.jpg)
PIC18F46K80T-I/ML
Manufacturer Part Number
PIC18F46K80T-I/ML
Description
ECAN, 64KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 44 QFN 8x8x0.9mm T/R
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K80-ISO.pdf
(628 pages)
Specifications of PIC18F46K80T-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
PIC18F46K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
35
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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REGISTER 21-2:
2011 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3-0
Note 1:
WCOL
R/W-0
2:
3:
In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by
writing to the SSPBUF register.
When enabled, these pins must be properly configured as inputs or outputs.
Bit combinations not specifically listed here are either reserved or implemented in I
WCOL: Write Collision Detect bit
1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in
0 = No collision
SSPOV: Receive Overflow Indicator bit
SPI Slave mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of over-
0 = No overflow
SSPEN: Master Synchronous Serial Port Enable bit
1 = Enables the serial port and configures SCK, SDO, SDI and SS as serial port pins
0 = Disables the serial port and configures these pins as I/O port pins
CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
SSPM<3:0>: Master Synchronous Serial Port Mode Select bits
1010 = SPI Master mode: clock = F
0101 = SPI Slave mode: clock = SCK pin; SS pin control disabled; SS can be used as I/O pin
0100 = SPI Slave mode: clock = SCK pin; SS pin control enabled
0011 = SPI Master mode: clock = TMR2 output/2
0010 = SPI Master mode: clock = F
0001 = SPI Master mode: clock = F
0000 = SPI Master mode: clock = F
SSPOV
R/W-0
software)
flow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the
SSPBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software).
SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE)
(1)
W = Writable bit
‘1’ = Bit is set
SSPEN
R/W-0
(2)
R/W-0
CKP
Preliminary
OSC
OSC
OSC
OSC
(1)
/8
/64
/16
/4
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC18F66K80 FAMILY
SSPM3
R/W-0
(2)
(3)
SSPM2
R/W-0
(3)
(3)
x = Bit is unknown
SSPM1
R/W-0
2
C mode only.
(3)
DS39977C-page 295
SSPM0
R/W-0
bit 0
(3)
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