PIC18F46K80T-I/ML Microchip Technology, PIC18F46K80T-I/ML Datasheet - Page 236
![ECAN, 64KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 44 QFN 8x8x0.9mm T/R](/photos/39/70/397090/qfn-44_sml.jpg)
PIC18F46K80T-I/ML
Manufacturer Part Number
PIC18F46K80T-I/ML
Description
ECAN, 64KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 44 QFN 8x8x0.9mm T/R
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K80-ISO.pdf
(628 pages)
Specifications of PIC18F46K80T-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
PIC18F46K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
35
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC18F66K80 FAMILY
16.5.4
When Timer3 Gate Single Pulse mode is enabled, it is
possible to capture a single pulse gate event. Timer3
Gate Single Pulse mode is first enabled by setting the
T3GSPM bit (T3GCON<4>). Next, the T3GGO/
T3DONE bit (T3GCON<3>) must be set.
The Timer3 will be fully enabled on the next increment-
ing edge. On the next trailing edge of the pulse, the
T3GGO/T3DONE bit will automatically be cleared. No
FIGURE 16-4:
DS39977C-page 236
Timer3
TMR3GIF
TMR3GE
T3GSPM
T3DONE
T3GPOL
T3GGO/
T3GVAL
T3G_IN
T3CKI
TIMER3 GATE SINGLE PULSE
MODE
TIMER3 GATE SINGLE PULSE MODE
N
Cleared by Software
Counting Enabled on
Set by Software
Rising Edge of T3G
Preliminary
N + 1
other gate events will be allowed to increment Timer3
until the T3GGO/T3DONE bit is once again set in
software.
Clearing the T3GSPM bit will also clear the T3GGO/
T3DONE bit. (For timing details, see
Simultaneously enabling the Toggle mode and the
Single Pulse mode will permit both sections to work
together. This allows the cycle times on the Timer3 gate
source to be measured. (For timing details, see
Figure
16-5.)
Set by Hardware on
Falling Edge of T3GVAL
Cleared by Hardware on
Falling Edge of T3GVAL
N + 2
2011 Microchip Technology Inc.
Figure
Software
Cleared by
16-4.)
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