PIC18F46K80T-I/ML Microchip Technology, PIC18F46K80T-I/ML Datasheet - Page 337
![ECAN, 64KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 44 QFN 8x8x0.9mm T/R](/photos/39/70/397090/qfn-44_sml.jpg)
PIC18F46K80T-I/ML
Manufacturer Part Number
PIC18F46K80T-I/ML
Description
ECAN, 64KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 44 QFN 8x8x0.9mm T/R
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K80-ISO.pdf
(628 pages)
Specifications of PIC18F46K80T-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
PIC18F46K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
35
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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TABLE 21-4:
2011 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
TRISC
SSPBUF
SSPADD
SSPMSK
SSPCON1
SSPCON2
SSPSTAT
PMD0
ODCON
Legend: — = unimplemented, read as ‘ 0 ’. Shaded cells are not used by the MSSP module in I
Note 1:
Name
2:
(1)
SSPMSK shares the same address in SFR space as SSPADD, but is only accessible in certain I
Slave operating modes in 7-Bit Masking mode. See
more details.
Alternate bit definitions for use in I
MSSP Address Register (I
MSSP Baud Rate Reload Register (I
MSSP Receive Buffer/Transmit Register
GIE/GIEH PEIE/GIEL
CCP5MD
OSCFIF
OSCFIE
OSCFIP
TRISC7
SSPOD
REGISTERS ASSOCIATED WITH I
WCOL
PSPIF
PSPIE
PSPIP
GCEN
GCEN
MSK7
Bit 7
SMP
ACKSTAT
ACKSTAT
CCP4MD
CCP5OD
TRISC6
SSPOV
MSK6
ADIF
ADIE
ADIP
Bit 6
CKE
—
—
—
ADMSK5
2
CCP3MD
CCP4OD
TMR0IE
C™ Slave mode),
TRISC5
SSPEN
ACKDT
RC1IF
RC1IE
RC1IP
MSK5
Bit 5
D/A
2
—
—
—
C Slave mode operations only.
(2)
Preliminary
2
C Master mode)
ADMSK4
CCP2MD
CCP3OD
TRISC4
ACKEN
INT0IE
TX1IF
TX1IE
TX1IP
MSK4
Bit 4
CKP
2
—
—
—
C™ OPERATION
P
PIC18F66K80 FAMILY
Section 21.4.3.4 “7-Bit Address Masking Mode”
(2)
ADMSK3
CCP1MD
CCP2OD
TRISC3
SSPM3
SSPIE
SSPIP
SSPIF
BCLIF
BCLIE
BCLIP
RCEN
MSK3
RBIE
Bit 3
S
(2)
ADMSK2
UART2MD UART1MD
TMR1GIE
TMR1GIP
TMR1GIF
CCP1OD
TMR0IF
HLVDIF
HLVDIE
HLVDIP
TRISC2
SSPM2
MSK2
Bit 2
PEN
R/W
(2)
ADMSK1
TMR2IF
TMR2IE
TMR2IP
TMR3IF
TMR3IE
TMR3IP
TRISC1
SSPM1
INT0IF
2
MSK1
RSEN
U2OD
Bit 1
C™ mode.
UA
DS39977C-page 337
(2)
TMR3GIF
TMR3GIE
TMR3GIP
2
TMR1IF
TMR1IE
TMR1IP
TRISC0
SSPMD
SSPM0
C™
U1OD
MSK0
RBIF
Bit 0
SEN
SEN
BF
for
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