PIC18F46K80T-I/ML Microchip Technology, PIC18F46K80T-I/ML Datasheet - Page 290
![ECAN, 64KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 44 QFN 8x8x0.9mm T/R](/photos/39/70/397090/qfn-44_sml.jpg)
PIC18F46K80T-I/ML
Manufacturer Part Number
PIC18F46K80T-I/ML
Description
ECAN, 64KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 44 QFN 8x8x0.9mm T/R
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K80-ISO.pdf
(628 pages)
Specifications of PIC18F46K80T-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
PIC18F46K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
35
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC18F66K80 FAMILY
FIGURE 20-16:
FIGURE 20-17:
FIGURE 20-18:
DS39977C-page 290
Note 1: Port outputs are configured as displayed when
STR<D:A>
P1<D:A>
Port Data
P1A Signal
STR<D:A>
Port Data
Port Data
Port Data
P1<D:A>
CCP1M1
CCP1M0
CCP1M1
CCP1M0
2: Single PWM output requires setting at least
PWM
STRA
STRB
STRC
STRD
PWM
the CCP1CON register bits, P1M<1:0> = 00
and CCP1M<3:2> = 11.
one of the STR<D:A> bits.
Port Data
SIMPLIFIED STEERING
BLOCK DIAGRAM
EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRSYNC = 0)
EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION (STRSYNC = 1)
1
0
1
0
1
0
1
0
PWM Period
Port Data
TRIS
TRIS
TRIS
TRIS
Output Pin
Output Pin
Output Pin
Output Pin
(1,2)
Preliminary
P1n = PWM
20.4.7.1
The STRSYNC bit of the PSTR1CON register gives the
user two choices for when the steering event will
happen. When the STRSYNC bit is ‘ 0 ’, the steering
event will happen at the end of the instruction that
writes to the PSTR1CON register. In this case, the out-
put signal at the P1<D:A> pins may be an incomplete
PWM waveform. This operation is useful when the user
firmware needs to immediately remove a PWM signal
from the pin.
When the STRSYNC bit is ‘ 1 ’, the effective steering
update will happen at the beginning of the next PWM
period. In this case, steering on/off the PWM output will
always produce a complete PWM waveform.
Figures
of the PWM steering depending on the STRSYNC
setting.
P1n = PWM
20-17
Steering Synchronization
and
20-18
2011 Microchip Technology Inc.
illustrate the timing diagrams
Port Data
Port Data
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