PIC16LF737-I/ML Microchip Technology, PIC16LF737-I/ML Datasheet - Page 40
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC16LF737-I/ML
Manufacturer Part Number
PIC16LF737-I/ML
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Specifications of PIC16LF737-I/ML
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC16F7X7
4.6.3
When clock switching is performed, the Watchdog
Timer is disabled because the Watchdog Ripple
Counter is used as the Oscillator Start-up Timer (OST).
REGISTER 4-2:
DS30498C-page 38
Note:
CLOCK TRANSITION AND WDT
The OST is only used when switching to
XT, HS and LP Oscillator modes.
bit 7
bit 6-4
bit 3
bit 2
bit 1-0
Unimplemented: Read as ‘0’
IRCF<2:0>: Internal RC Oscillator Frequency Select bits
000 = 31.25 kHz
001 = 125 kHz
010 = 250 kHz
011 = 500 kHz
100 = 1 MHz
101 = 2 MHz
110 = 4 MHz
111 = 8 MHz
OSTS: Oscillator Start-up Time-out Status bit
1 = Device is running from the primary system clock
0 = Device is running from the Timer1 oscillator (T1OSC) or INTRC as a secondary system clock
IOFS: INTOSC Frequency Stable bit
1 = Frequency is stable
0 = Frequency is not stable
SCS<1:0>: Oscillator Mode Select bits
00 = Oscillator mode defined by FOSC<2:0>
01 = T1OSC is used for system clock
10 = Internal RC is used for system clock
11 = Reserved
bit 7
Legend:
R = Readable bit
-n = Value at POR
OSCCON: OSCILLATOR CONTROL REGISTER (ADDRESS 8Fh)
Note 1: Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the oscillator
U-0
—
mode.
R/W-0
IRCF2
R/W-0
IRCF1
W = Writable bit
‘1’ = Bit is set
IRCF0
R/W-0
Once the clock transition is complete (i.e., new oscilla-
tor selection switch has occurred), the Watchdog
Counter is re-enabled with the Counter Reset. This
allows the user to synchronize the Watchdog Timer to
the start of execution at the new clock frequency.
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
OSTS
R-0
(1)
IOFS
R-0
2004 Microchip Technology Inc.
x = Bit is unknown
R/W-0
SCS1
R/W-0
SCS0
bit 0
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