PIC16LF737-I/ML Microchip Technology, PIC16LF737-I/ML Datasheet - Page 104
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC16LF737-I/ML
Manufacturer Part Number
PIC16LF737-I/ML
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Specifications of PIC16LF737-I/ML
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC16F7X7
10.4
The MSSP module in I
master and slave functions (including general call
support) and provides interrupts on Start and Stop bits
in hardware to determine a free bus (multi-master
function). The MSSP module implements the standard
mode specifications, as well as 7-bit and 10-bit
addressing.
Two pins are used for data transfer:
• Serial clock (SCL) – RC3/SCK/SCL
• Serial data (SDA) – RC4/SDI/SDA
The user must configure these pins as inputs or outputs
through the TRISC<4:3> bits.
FIGURE 10-7:
DS30498C-page 102
RC3/SCK/
RC4/
SDI/
SDA
SCL
I
2
C Mode
Read
Shift
Clock
MSb
MSSP BLOCK DIAGRAM
(I
Stop bit Detect
SSPADD Reg
Match Detect
SSPBUF Reg
SSPSR Reg
2
2
Start and
C mode fully implements all
C™ MODE)
LSb
Write
Internal
Data Bus
Set, Reset
S, P bits
(SSPSTAT Reg)
Addr Match
10.4.1
The MSSP module has six registers for I
These are:
• MSSP Control Register (SSPCON)
• MSSP Control Register 2 (SSPCON2)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• MSSP Shift Register (SSPSR) – Not directly
• MSSP Address Register (SSPADD)
SSPCON, SSPCON2 and SSPSTAT are the control
and status registers in I
SSPCON and SSPCON2 registers are readable and
writable. The lower 6 bits of the SSPSTAT are
read-only. The upper two bits of the SSPSTAT are
read/write.
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
SSPADD register holds the slave device address when
the SSP is configured in I
SSP is configured in Master mode, the lower seven bits
of SSPADD act as the Baud Rate Generator reload
value.
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During transmission, the SSPBUF is not double-
buffered. A write to SSPBUF will write to both SSPBUF
and SSPSR.
accessible
REGISTERS
2004 Microchip Technology Inc.
2
2
C Slave mode. When the
C mode operation. The
2
C operation.
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