PIC16LF737-I/ML Microchip Technology, PIC16LF737-I/ML Datasheet - Page 238
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC16LF737-I/ML
Manufacturer Part Number
PIC16LF737-I/ML
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Specifications of PIC16LF737-I/ML
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC16F7X7
FIGURE 18-20:
TABLE 18-16: A/D CONVERSION REQUIREMENTS
DS30498C-page 236
130
131
132
134
Note 1:
Param
No.
Note: If the A/D clock source is selected as RC, a time of T
A/D DATA
SAMPLE
A/D CLK
2:
ADRES
*
†
§
T
T
T
T
Symbol
BSF ADCON0, GO
AD
CNV
ACQ
GO
ADIF
GO
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
This specification ensured by design.
ADRES register may be read on the following T
See Section 12.1 “A/D Acquisition Requirements” for minimum conditions.
Q4
instruction to be executed.
A/D Clock Period
Conversion Time (not including S/H time)
(Note 1)
Acquisition Time
Q4 to A/D Clock Start
132
A/D CONVERSION TIMING
Characteristic
(T
OSC
/2)
9
(1)
PIC16F7X7
PIC16LF7X7
PIC16F7X7
PIC16LF7X7
8
OLD_DATA
Sampling Stopped
7
CY
(Note 2)
cycle.
CY
Min
10*
1.6
3.0
2.0
3.0
—
is added before the A/D clock starts. This allows the SLEEP
130
131
T
OSC
Typ†
4.0
6.0
40
—
—
—
—
/2 §
2
Max
6.0
9.0
—
—
12
—
—
—
1
Units
T
—
AD
s
s
s
s
s
s
1 T
0
2004 Microchip Technology Inc.
CY
T
T
A/D RC mode
A/D RC mode
The minimum time is the
amplifier settling time. This may
be used if the “new” input
voltage has not changed by
more than 1 LSb (i.e., 5.0 mV @
5.12V) from the last sampled
voltage (as stated on C
If the A/D clock source is
selected as RC, a time of T
added before the A/D clock
starts. This allows the SLEEP
instruction to be executed.
OSC
OSC
based, V
based, V
DONE
NEW_DATA
Conditions
REF
REF
3.0V
2.0V
HOLD
CY
).
is
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