PIC16LF737-I/ML Microchip Technology, PIC16LF737-I/ML Datasheet - Page 26
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC16LF737-I/ML
Manufacturer Part Number
PIC16LF737-I/ML
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Specifications of PIC16LF737-I/ML
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC16F7X7
2.2.2.4
The PIE1 register contains the individual enable bits for
the peripheral interrupts.
REGISTER 2-4:
DS30498C-page 24
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PIE1 Register
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS 8Ch)
bit 7
PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt
RCIE: AUSART Receive Interrupt Enable bit
1 = Enables the AUSART receive interrupt
0 = Disables the AUSART receive interrupt
TXIE: AUSART Transmit Interrupt Enable bit
1 = Enables the AUSART transmit interrupt
0 = Disables the AUSART transmit interrupt
SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Legend:
R = Readable bit
-n = Value at POR
PSPIE
R/W-0
Note 1: PSPIE is reserved on 28-pin devices; always maintain this bit clear.
(1)
R/W-0
ADIE
R/W-0
RCIE
W = Writable bit
‘1’ = Bit is set
R/W-0
TXIE
Note:
SSPIE
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
(1)
CCP1IE
R/W-0
2004 Microchip Technology Inc.
TMR2IE
x = Bit is unknown
R/W-0
TMR1IE
R/W-0
bit 0
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