PIC16F1526T-I/PT Microchip Technology, PIC16F1526T-I/PT Datasheet - Page 184

• Manufacturer Part Number: PIC16F1526T-I/PT
• Description: 64-pin, 14KB Flash, 768B RAM, 10-bit ADC, 10xCCP, 2xSPI, 2xMI2C, 2xEUSART, 2.3V-
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1526T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 5.5 V
• Data Converters: A/D 30x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16(L)F1526/27
20.1
The Capture mode function described in this section is
available and identical for CCP modules.
Capture mode makes use of the 16-bit Timer1/3/5
resource. When an event occurs on the CCPx pin, the
16-bit CCPRxH:CCPRxL register pair captures and
stores the 16-bit value of the TMRxH:TMRxL register
pair, respectively. An event is defined as one of the
following and is configured by the CCPxM<3:0> bits of
the CCPxCON register:
• Every falling edge
• Every rising edge
• Every 4th rising edge
• Every 16th rising edge
When a capture is made, the Interrupt Request flag bit
CCPxIF of the PIRx register is set. The interrupt flag
must be cleared in software. If another capture occurs
before the value in the CCPRxH, CCPRxL register pair
is read, the old captured value is overwritten by the new
captured value.
Figure 20-1
operation.
20.1.1
In Capture mode, the CCPx pin should be configured
as an input by setting the associated TRIS control bit.
Also, the CCP2x pin function can be moved to
alternative pins using the APFCON register. Refer to
Section 12.1 “Alternate Pin Function”
details.
FIGURE 20-1:
DS41458B-page 184
CCPx
Pin
Note:
System Clock (F
Capture Mode
Edge Detect
CCP PIN CONFIGURATION
If the CCPx pin is configured as an output,
a write to the port can cause a capture
condition.
Prescaler
 1, 4, 16
shows a simplified diagram of the Capture
and
CCPxM<3:0>
OSC
)
Set Flag bit CCPxIF
(PIRx register)
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
Capture
Enable
CCPRxH
TMRxH
CCPRxL
for more
TMRxL
Preliminary
20.1.2
Timer1/3/5 must be running in Timer mode or
Synchronized Counter mode for the CCP module to use
the capture feature. In Asynchronous Counter mode, the
capture operation may not work.
See
Control”
Timer1/3/5.
TABLE 20-1:
20.1.3
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCPxIE interrupt enable bit of the PIEx register clear to
avoid false interrupts. Additionally, the user should
clear the CCPxIF interrupt flag bit of the PIRx register
following any change in Operating mode.
CCP10
Section 18.0 “Timer1/3/5 Module with Gate
CCP1
CCP2
CCP3
CCP4
CCP5
CCP6
CCP7
CCP8
CCP9
CCP
for
TIMER1/3/5 MODE RESOURCE
SOFTWARE INTERRUPT MODE
more
CCPx CAPTURE TIMER1/3/5
RESOURCES
TMR1
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 2011 Microchip Technology Inc.
information
TMR3
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on
configuring
TMR5
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