PIC16F1526T-I/PT Microchip Technology, PIC16F1526T-I/PT Datasheet - Page 171

• Manufacturer Part Number: PIC16F1526T-I/PT
• Description: 64-pin, 14KB Flash, 768B RAM, 10-bit ADC, 10xCCP, 2xSPI, 2xMI2C, 2xEUSART, 2.3V-
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1526T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 5.5 V
• Data Converters: A/D 30x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

18.6.2
The Timer1/3/5 gate source can be selected from one
of four different sources. Source selection is controlled
by the TxGSS bits of the TxGCON register. The polarity
for each available source is also selectable. Polarity
selection is controlled by the TxGPOL bit of the
TxGCON register.
TABLE 18-4:
18.6.2.1
The TxG pin is one source for Timer1/3/5 gate control.
It can be used to supply an external source to the
Timer1/3/5 gate circuitry.
18.6.2.2
When Timer0 increments from FFh to 00h, a
low-to-high pulse will automatically be generated and
internally supplied to the Timer1/3/5 gate circuitry.
18.6.3
When Timer1/3/5 Gate Toggle mode is enabled, it is
possible to measure the full-cycle length of a
Timer1/3/5 gate signal, as opposed to the duration of a
single level pulse.
The Timer1/3/5 gate source is routed through a flip-flop
that changes state on every incrementing edge of the
signal. See
Timer1/3/5 Gate Toggle mode is enabled by setting the
TxGTM bit of the TxGCON register. When the TxGTM
bit is cleared, the flip-flop is cleared and held clear. This
is necessary in order to control which edge is
measured.
 2011 Microchip Technology Inc.
T1GSS
Note:
00
01
10
11
T1G Pin
Timer2 match PR2
(TMR2 increments to match PR2)
TIMER1/3/5 GATE SOURCE
SELECTION
TIMER1/3/5 GATE TOGGLE MODE
Figure 18-5
Enabling Toggle mode at the same time
as changing the gate polarity may result in
indeterminate operation.
TxG Pin Gate Operation
Timer0 Overflow Gate Operation
Timer1 Gate Source
TIMER1/3/5 GATE SOURCES
for timing details.
(TMR0 increments from FFh to 00h)
T3G Pin
Timer4 match PR4
Preliminary
Timer10 match PR10
Timer3 Gate Source
Overflow of Timer0
18.6.4
When Timer1/3/5 Gate Single-Pulse mode is enabled, it
is possible to capture a single pulse gate event.
Timer1/3/5 Gate Single-Pulse mode is first enabled by
setting the TxGSPM bit in the TxGCON register. Next,
the TxGGO/DONE bit in the TxGCON register must be
set. The Timer1/3/5 will be fully enabled on the next
incrementing edge. On the next trailing edge of the pulse,
the TxGGO/DONE bit will automatically be cleared. No
other gate events will be allowed to increment Timer1/3/5
until the TxGGO/DONE bit is once again set in software.
See
If the Single Pulse Gate mode is disabled by clearing the
TxGSPM bit in the TxGCON register, the TxGGO/DONE
bit should also be cleared.
Enabling the Toggle mode and the Single-Pulse mode
simultaneously will permit both sections to work
together. This allows the cycle times on the Timer1/3/5
gate source to be measured. See
details.
18.6.5
When Timer1/3/5 Gate Value Status is utilized, it is pos-
sible to read the most current level of the gate control
value. The value is stored in the TxGVAL bit in the
TxGCON register. The TxGVAL bit is valid even when
the Timer1/3/5 gate is not enabled (TMRxGE bit is
cleared).
Figure 18-6
PIC16(L)F1526/27
TIMER1/3/5 GATE SINGLE-PULSE
MODE
TIMER1/3/5 GATE VALUE STATUS
for timing details.
T5G Pin
Timer6 match PR6
Timer5 Gate Source
Figure 18-7
DS41458B-page 171
for timing