PIC16F1526T-I/PT Microchip Technology, PIC16F1526T-I/PT Datasheet - Page 102

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PIC16F1526T-I/PT

Manufacturer Part Number
PIC16F1526T-I/PT
Description
64-pin, 14KB Flash, 768B RAM, 10-bit ADC, 10xCCP, 2xSPI, 2xMI2C, 2xEUSART, 2.3V-
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheet

Specifications of PIC16F1526T-I/PT

Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 5.5 V
Data Converters
A/D 30x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F1526T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC16F1526T-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC16(L)F1526/27
TABLE 11-1:
11.2.1
To read a program memory location, the user must:
1.
2.
3.
Once the read control bit is set, the program memory
Flash controller will use the second instruction cycle to
read the data. This causes the second instruction
immediately following the “BSF PMCON1,RD” instruction
to be ignored. The data is available in the very next cycle,
in the PMDATH:PMDATL register pair; therefore, it can
be read as two bytes in the following instructions.
PMDATH:PMDATL register pair will hold this value until
another read or until it is written to by the user.
DS41458B-page 102
Note:
PIC16(L)F1526
PIC16(L)F1527
Write
PMADRH:PMADRL register pair.
Clear the CFGS bit of the PMCON1 register.
Then, set control bit RD of the PMCON1 register.
Device
READING THE FLASH PROGRAM
MEMORY
The two instructions following a program
memory read are required to be NOPs.
This prevents the user from executing a
two-cycle
instruction after the RD bit is set.
the
FLASH MEMORY
ORGANIZATION BY DEVICE
desired
instruction
Row Erase
(words)
32
address
on
Latches
(words)
the
to
Write
32
the
next
Preliminary
FIGURE 11-1:
Program or Configuration Memory
Instruction Fetched ignored
Instruction Fetched ignored
Initiate Read Operation
NOP execution forced
(PMADRH:PMADRL)
NOP execution forced
PMDATH:PMDATL
Data read now in
Read Operation
Read Operation
Word Address
FLASH PROGRAM
MEMORY READ
FLOWCHART
 2011 Microchip Technology Inc.
(RD = 1)
(CFGS)
Select
Select
Start
End

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