HBLXT9763HC.C4 Intel, HBLXT9763HC.C4 Datasheet - Page 28

• Manufacturer Part Number: HBLXT9763HC.C4
• Manufacturer: Intel

Specifications of HBLXT9763HC.C4

• Lead Free Status / RoHS Status: Not Compliant

LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII
1.10
1.10.1
28
100 Mbps
10 Mbps
1. Test Loopback is enabled when 0.14 = 1
Replaced by
/J/K/ code-groups
Start-of-Stream
Delimiter (SSD)
P0
Speed
Table 8.
Figure 13. 100BASE-X Frame Format
64-Bit Preamble
P1
(8 Octets)
Full-Duplex
Half-Duplex
Full-Duplex
Half-Duplex, 16.8 = 0
Half-Duplex, 16.8 = 1
P6
Carrier Sense, Loopback, and Collision Conditions
100 Mbps Operation
100BASE-X Network Operations
During 100BASE-X operation, the LXT9763 transmits and receives 5-bit symbols across the
network link.
actively transmitting data, the LXT9763 sends out Idle symbols on the line.
As shown in
LXT9763 detects the start of preamble, it transmits a J/K Start-of-Stream Delimiter (SSD) symbol
to the network. It then encodes and transmits the rest of the packet, including the balance of the
preamble, the Start-of-Frame Delimiter (SFD), packet data, and CRC. Once the packet ends, the
LXT9763 transmits the T/R End-of-Stream Delimiter (ESD) symbol and then returns to
transmitting Idle symbols.
In 100TX mode, the LXT9763 scrambles the data and transmits it to the network using MLT-3 line
code. The MLT-3 signals received from the network are descrambled and decoded and sent across
the MII to the MAC.
interface.
In 100FX mode, the LXT9763 transmits and receives NRZI signals across the PECL interface. An
external 100FX transceiver module is required to complete the fiber connection.
Duplex Condition
Delimiter (SFD)
Start-of-Frame
SFD
DA
Figure
Figure 13
Address (6 Octets each)
Destination and Source
DA
13, the MAC starts each transmission with a preamble pattern. As soon as the
Figure 14
Transmit or Receive
Transmit or Receive
Transmit or Receive
SA
shows the structure of a standard frame packet. When the MAC is not
Carrier Sense
Receive Only
Receive Only
SA
shows the internal signal flow between the MII and the network
Packet Length
L1
(2 Octets)
L2
Loopback
(Pad to minimum packet size)
D0
Test
None
Yes
Yes
No
No
1
Data Field
D1
Dn
Operational
Loopback
Yes
Frame Check Field
No
No
No
No
(4 Octets)
CRC
End-of-Stream Delimiter (ESD)
/T/R/ code-groups
Transmit and Receive
Transmit and Receive
Transmit and Receive
Replaced by
InterFrame Gap / Idle Code
I0
Collision
(> 12 Octets)
None
None
Datasheet
IFG