HBLXT9763HC.C4 Intel, HBLXT9763HC.C4 Datasheet - Page 23
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HBLXT9763HC.C4
Manufacturer Part Number
HBLXT9763HC.C4
Description
Manufacturer
Intel
Datasheet
1.HBLXT9763HC.C4.pdf
(74 pages)
Specifications of HBLXT9763HC.C4
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1.7
.
Datasheet
1. These pins set the default values for registers 0 and 4 accordingly.
2. X = Don’t Care.
3. Do not select Fiber mode with Auto-Negotiation enabled.
AutoNeg
Enabled
Disabled
Mode
Figure 9. Hardware Configuration Settings
Table 7. Hardware Configuration Settings
Desired Configuration
Note: Fiber operation cannot be selected via hardware. Fiber operation must be enabled via the MDIO
3
Speed
10/100
Mode
100
100
10
Hardware Configuration Settings
The LXT9763 provides a hardware option to set the initial device configuration. The hardware
option uses the three LED/CFG pins for each port. This provides three control bits per port, as
listed in
in
configure for either open drain or open source circuits (10 mA max current rating) as required by
the hardware configuration. In applications where all ports are configured the same, several pins
may be tied together with a single resistor.
port.
Figure
LED/CFG Pin
LED/CFG Pin
Duplex
Mode
Table
Half
Half
Half
Half
Full
Full
Full
Full
9. The LED pins are sensitive to polarity and will automatically pull up or pull down to
1. LEDs will automatically correct
their polarity upon power-up or
7. The LED drivers can operate as either open drain or open source circuits as shown
1
0
0
0
0
1
1
1
1
LED/CFGn_
Pin Settings
Configuration Bit = 0
Configuration Bit = 1
Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763
2
0
0
1
1
0
0
1
1
1
3
0
1
0
1
0
1
0
1
AutoNeg
0.12
0
1
Control Register
VCC
Speed
0.13
0
1
1
Resulting Register Bit Values
FD
0.8
0
1
0
1
0
1
0
1
100FD
4.8
0
1
0
1
AN Advertisement Register
Auto-Negotiation
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100TX
4.7
X X X X
1
10 FD
2
4.6
0
0
1
10T
4.5
0
1
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