HBLXT9763HC.C4 Intel, HBLXT9763HC.C4 Datasheet - Page 20

• Manufacturer Part Number: HBLXT9763HC.C4
• Manufacturer: Intel

Specifications of HBLXT9763HC.C4

• Lead Free Status / RoHS Status: Not Compliant

LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII
1.3.1
1.3.2
1.4
1.4.1
20
(Write)
Force Interrupt
1. Interrupt (Event) Status Register is cleared on read.
2. X = Any Interrupt capability
MDIO
Event X Enable Reg
Event X Status Reg
MDC
Figure 6. Management Interface Write Frame Structure
Figure 7. Interrupt Logic
Idle
Per Event
Preamble
32 "1"s
. .
.
Hardware Control Interface
The LXT9763 provides a Hardware Control Interface for applications where the MDIO is not
desired. The Hardware Control Interface consists of three Configuration (CFG) pins for each port.
The CFG pins double as LED drivers. Refer to
additional details.
MII Data Interface
The LXT9763 supports six standard MIIs (one per port). The MII consists of a data interface and a
management interface. The MII Data Interface passes data between the LXT9763 and one or more
Media Access Controllers (MACs). Separate parallel buses are provided for transmit and receive.
This interface operates at either 2.5 MHz or 25 MHz. The speed is set automatically, once the
operating conditions of the network link have been determined.
Operating Requirements
Power Requirements
The LXT9763 requires four power supply inputs, VCCD, VCCR, VCCT, and VCCIO. The digital
and analog circuits require 3.3 V supplies (VCCD, VCCR and VCCT). These inputs may be
supplied from a single source although decoupling is required to each respective ground.
0
ST
1
AND
0
Op Code
1
Interrupt Enable
OR
A4
PHY Address
A3
AND
A0
Write
R4
Register Address
R3
“Hardware Configuration Settings” on page 23
R0
1
Per port
Around
Turn
. .
.
0
D15
Port
Combine
Logic
D14
Data
D1
D0
Interrupt Pin
Datasheet
Idle
for