FLLXT1000BA.C4QE000 Intel, FLLXT1000BA.C4QE000 Datasheet - Page 6

• Manufacturer Part Number: FLLXT1000BA.C4QE000
• Manufacturer: Intel

Specifications of FLLXT1000BA.C4QE000

• Lead Free Status / RoHS Status: Not Compliant

Contents
5.0
6.0
A
Figures
6
Register Set
Mechanical Specification
Ordering Information
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LXT1000 Block Diagram ..................................................................................... 11
LXT1000 PBGA Assignments ............................................................................. 12
LXT1000 Applications ......................................................................................... 22
LXT1000 Block Diagram ..................................................................................... 23
Crossover Function ............................................................................................. 24
GMII Data Interface............................................................................................. 27
Serial Interface .................................................................................................... 28
Relationship between 10 Mbps Serial Interface and 10 Mbps MII Interface ....... 28
10-Bit Interface (TBI)........................................................................................... 29
Data Flow Between PHY and Mac...................................................................... 30
MDIO Read Frame Format ................................................................................. 32
MDIO Write Frame Format.................................................................................. 32
Interrupt Handling................................................................................................ 33
Quick Status Register ......................................................................................... 35
PHY Address Determination via LED balls ......................................................... 36
Overview of Link Establishment .......................................................................... 40
Link Speed and Corresponding Clock Frequency Changes ............................... 46
1000BASE-T Functions Overview....................................................................... 47
1000BASE-T Transmit Flow and Line Coding Scheme ...................................... 49
1000BASE-T Receive Flow................................................................................. 50
1000BASE-T Frame Structure ............................................................................ 52
1000BASE-T Transmission (No Errors, No Collision, No Carrier Extension)...... 53
1000BASE-T Reception (No Errors, No Collision, No Carrier Extension)........... 53
1000BASE-T Transmission with Collision........................................................... 53
1000BASE-T False Carrier Detection ................................................................. 54
1000BASE-T Transmission with Error ................................................................ 54
1000BASE-T Reception with Error...................................................................... 55
1000BASE-T Transmission, Carrier Extend and Packet Concatenation ............ 56
1000BASE-T Reception, Carrier Extension and Packet Concatenation ............. 56
1000BASE-T Transmission Extend - Packet Concatenation and Carrier Extension,
with Errors57
1000BASE-T Reception Extend - Packet Concatenation and Carrier Extension,
with Errors57
Protocol Sublayers and Associated Functions.................................................... 58
100BASE-TX Frame Structure............................................................................ 60
100BASE-TX Data Flow...................................................................................... 60
100BASE-T Reception (No Errors, No Collision, No Carrier Extension)............. 62
100BASE-TX Transmission with Collision .......................................................... 62
100BASE-T Transmission (No Errors, No Collision, No Carrier Extension)........ 62
Master/Slave Relationship .................................................................................. 68
Typical MII/GMII Interface ................................................................................... 72
Typical Configuration - GMII Interface ................................................................ 73
................................................................................................................ 90
............................................................................................ 106
.................................................................................... 105
Document #: 249276
Rev. Date: 07/20/01
Revision #: 002
Datasheet