FLLXT1000BA.C4QE000 Intel, FLLXT1000BA.C4QE000 Datasheet - Page 31

• Manufacturer Part Number: FLLXT1000BA.C4QE000
• Manufacturer: Intel

Specifications of FLLXT1000BA.C4QE000

• Lead Free Status / RoHS Status: Not Compliant

2.3.4.2
2.3.5
2.3.6
Datasheet
Document #: 249276
Revision #: 002
Rev. Date: 07/20/01
Receive Mode – Data Traffic from PHY to MAC
The MAC receives encapsulated data from the PHY-TBI interface according to the IEEE 802.3z
specification. The PHY appends a single, additional /R/ to the code-group stream to all frames that
end in an even byte. This action ensures that the subsequent /I/ is aligned on an even-numbered
code-group boundary for data transmission from the PHY to the MAC and results in the addition of
a one-byte carrier extend.
MAC Data Interface Control
The MAC Interface can be controlled via Tristate Condition and Auto-Negotiation Isolation:
MDIO/MDC Management Interface
The LXT1000 supports the IEEE compliant Management Data Input/Output (MDIO) Interface,
which allows the MAC or management control function to manage the LXT1000 by accessing its
internal control and status registers (herein referred to as the “MII Registers”).
The MII register set is a block of 32 registers, each 16 bits wide. The MDIO interface provides
access to individual registers within the set. Certain registers are defined by the IEEE 802.3 and are
required for compliance (0-10, 15). Other registers are left open for vendor-specific
implementation. The LXT1000 implements all the required registers, and additional registers (16-
21) for device-specific enhancements.
The basic physical interface consists of two signals: the bidirectional data line (MDIO) and a clock
line (MDC), driven by the MAC or management function. This interface allows the MAC to
manage up to 32 PHYs. All transfers are initiated by the MAC. The MDIO protocol provides both
read and write operations (see
the MDIO line for the entire frame. For a read operation, a turn-around time is inserted in the frame
to allow the PHY to drive data back to the MAC. The LXT1000 supports a maximum frequency on
MDC of 2.5 MHz.
The MDIO frame structure starts with a 32-bit preamble, which is required by the LXT1000. It
includes a start-of-frame marker, an op-code, a 10-bit address field, and a 16-bit data field. The
address field is divided into two 5-bit segments. The first segment identifies the PHY and the
second identifies the register being accessed. The PHY address that the LXT1000 responds to is
configured via the Hardware Control Interface (refer to
page
The LXT1000 provides two enhancements to the basic MDIO interface: a disable function and an
external interrupt. The MDDIS input controls MDIO interface operation. Pulling MDDIS High
disables read and write operations on the MDIO. When pulled Low, both read and write operations
are allowed.
•
•
Tri-state Condition. Setting the Isolate Bit (0.10 = 1) forces the LXT1000 to tri-state all the
MAC Interface signals that it drives, including TX_CLK and RX_CLK. In this mode, the
MDIO and MDINT outputs are not tri-stated, so that the LXT1000 can continue to respond to
MAC management requests and send interrupts.
Auto-Negotiation Isolation. If the Auto-Negotiation Isolation feature is enabled (via Bit
16.2 = 1), the LXT1000 disables the MAC Interface when the link drops and then re-
negotiates to a different speed. The LXT1000 holds all data transfers to/from the MAC until
the MAC writes bit 16.2 = 0. (Refer to
36).
Figure 11
and
“Auto-Negotiate Isolation” on page
Figure
Gigabit Ethernet Transceiver — LXT1000
12). During a write operation, the MAC drives
“PHY Address Determination” on
44.)
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