FLLXT1000BA.C4QE000 Intel, FLLXT1000BA.C4QE000 Datasheet - Page 29

• Manufacturer Part Number: FLLXT1000BA.C4QE000
• Manufacturer: Intel

Specifications of FLLXT1000BA.C4QE000

• Lead Free Status / RoHS Status: Not Compliant

2.3.4
Datasheet
Document #: 249276
Revision #: 002
Rev. Date: 07/20/01
Figure 9. 10-Bit Interface (TBI)
RX_ER,RX_DV,RXD<7:0>
TX_ER,TX_EN,TXD<7:0>
LXT1000
The LXT1000’s TBI Mode does not support the signals SIGDET, EN_WRAP, or EN_COMDET.
All 10-bit I/Os are multiplexed onto the GMII lines as shown in
Interface is configured via the TENBIT pin.
When using this mode, the LXT1000 must be configured as shown below:
MAC auto-negotiation functions should be disabled. The MAC determines link status and its
partners abilities via the MDIO interface and the LXT1000 MII Registers.
TBI Communication Between MAC and PHY
The Ten-Bit Interface (TBI) is included in the IEEE 802.3z specification and was developed to
operate over fiber media. When used to operate over twisted-pair media, TBI displays
inconsistencies between the IEEE 802.3z and IEEE 802.3ab specifications. For example, the
physical- coding sublayer (PCS) appends a single, additional /R/ to the code-group stream to
ensure that the subsequent /I/ is aligned on an even-numbered, code-group boundary for data
transmission from the PHY to the MAC. (See IEEE 802.3z Clause 36.2.4.15.1 for more
information.) This action results in the addition of a one-byte carrier extend, which the MAC may
interpret as an error in approximately half of the transmitted frames.
•
•
•
•
•
•
Two 62.5 MHz clock (RBC0 and RBC1) in the receive direction
10-bit-wide interface
125 MHz clock on the GTX_CLK pin in the transmit direction
AN_EN set High
DUPLEX set High
SPEED<2:0> set High, Low, Low, respectively
GTX_CLK
RX_CLK
CRS
COL
REFCLK
EN_COMDET
TXD(9:0)
COMDET
SIGDET
RX(9:0)
RBC0
RBC1
EN_WRAP
Gigabit Ethernet Transceiver — LXT1000
Table 12
and
Table
MAC
13. The 10-Bit
29