FLLXT1000BA.C4QE000 Intel, FLLXT1000BA.C4QE000 Datasheet - Page 5

• Manufacturer Part Number: FLLXT1000BA.C4QE000
• Manufacturer: Intel

Specifications of FLLXT1000BA.C4QE000

• Lead Free Status / RoHS Status: Not Compliant

3.0
4.0
Datasheet
Document #: 249276
Revision #: 002
Rev. Date: 07/20/01
2.7
2.8
Application Information
3.1
3.2
3.3
3.4
3.5
Test Specifications
4.1
4.2
4.3
4.4
4.5
4.6
10 Mbps Operation..............................................................................................62
2.7.1
2.7.2
2.7.3
2.7.4
2.7.5
2.7.6
2.7.7
LXT1000 Operating Requirements......................................................................64
2.8.1
2.8.2
2.8.3
2.8.4
Design Recommendations ..................................................................................66
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.1.6
3.1.7
3.1.8
Test Information ..................................................................................................70
3.2.1
3.2.2
3.2.3
Magnetics Information .........................................................................................71
Component Manufacturers..................................................................................71
Typical Application Circuitry ................................................................................72
3.5.1
1000BASE-T Timing Parameters ........................................................................78
100BASE-TX Timing Parameters........................................................................80
10BASE-T Timing Parameters ............................................................................82
Auto-Negotiation Timing Parameters ..................................................................87
MDIO Timing Parameters....................................................................................88
QSTAT Timing Parameters .................................................................................89
Transmitting/Receiving...........................................................................63
Polarity Correction..................................................................................63
Link Test.................................................................................................63
Link Failure.............................................................................................63
SQE (Heartbeat).....................................................................................63
Jabber ....................................................................................................64
Preamble Generation Mode ...................................................................64
Power .....................................................................................................64
Clock ......................................................................................................64
RBIAS.....................................................................................................64
GBIAS ....................................................................................................65
Device Placement ..................................................................................66
Ground Plane Layout .............................................................................66
Power Plane Layout and Filtering ..........................................................66
3.1.3.1 Decoupling Capacitors ..............................................................67
RBIAS and GBIAS Requirements ..........................................................67
Twisted-Pair Layout................................................................................67
MAC Interface Layout.............................................................................67
5V Tolerance Considerations .................................................................67
Master/Slave Relationship Details..........................................................68
3.1.8.1 Configuring Master/Slave in Software .......................................68
3.1.8.2 Configuring Master/Slave in Hardware......................................69
3.1.8.3 Resolution of the Master/Slave Relationship.............................69
Forced Gig Operation.............................................................................70
Gigabit Transmit Test Clock ...................................................................70
Scrambler/Encoder Disable (100M) .......................................................70
Typical NIC Application ..........................................................................72
..................................................................................................75
.........................................................................................66
Contents
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