FLLXT1000BA.C4QE000 Intel, FLLXT1000BA.C4QE000 Datasheet - Page 45

• Manufacturer Part Number: FLLXT1000BA.C4QE000
• Manufacturer: Intel

Specifications of FLLXT1000BA.C4QE000

• Lead Free Status / RoHS Status: Not Compliant

2.4.10
2.4.10.1
Datasheet
Document #: 249276
Revision #: 002
Rev. Date: 07/20/01
Both ASM_DIR = 1
Either or both ASM_DIR = 0
ASM_DIR settings Local
(4.11) and Remote (5.10)
Table 23. Pause and Asymmetric Pause Settings
Notes: 1. RX_CLK and TX_CLK do not change frequency when the link state changes from auto-
Link Speed Changes
The LXT1000 is designed with glitch-free muxing logic, which guarantees that the two output
clocks, TX_CLK and RX_CLK, do not glitch during a speed change, for example, from Gigabit
operation to auto-negotiation. The changeover takes no more than three clock cycles of the slowest
clock (whether switching to or from). No clock pulse is shorter than the half-duty cycle of the
fastest clock (4 ns). During the transition phase, legitimate clock pulses of either speed may appear
on the outputs. There also may be no activity on the output for the entire duration of the transition.
How Link Speed Changes Affect MAC Interface Clock Signals
Whenever link speed changes occur, the frequencies of the MAC interface clock (TX_CLK and
RX_CLK) change accordingly.
clock frequency changes: Gigabit to auto-negotiation to 10BASE-T (Serial mode), and 100BASE-
T to auto-negotiation to 10BASE-T (MII mode). Many other link speed/clock changes are possible;
these only serve as examples.
negotiation to 10BASE-T and the MAC Interface is configured for 10 MII mode.
1
1
0
0
1
Either or both = 0
Setting -
Pause
Local
(4.10)
1
0
1
0
1
Pause Setting -
Remote
Figure 17
(5.10)
shows two link speed changes and the corresponding
Symmetric - Either side can flow control the other
Asymmetric - Remote can flow control local only
Asymmetric - Local can flow control remote
No flow control
Symmetric - Either side can flow control the other
No flow control
Gigabit Ethernet Transceiver — LXT1000
Result
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