AM79C976KI AMD (ADVANCED MICRO DEVICES), AM79C976KI Datasheet - Page 88

• Manufacturer Part Number: AM79C976KI
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C976KI

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / RoHS Status: Not Compliant

Auto-Negotiation goes further by providing a message-
based communication scheme called, Next Pages, be-
fore connecting to the Link Partner. The Network Port
Manager does not support this feature. However, the
host CPU can disable the Network Port Manager and
manage Next Pages by accessing the PHY device
through the PHY Access Register. The host CPU can
disable the Network Port Manager by setting the Dis-
able Port Manager (DISPM) bit (CMD3, bit 14) to 1.
(The DISPM bit corresponds to the Disable Auto-Nego-
tiation Auto Setup (DANAS) bit in BCR32 of older
PCnet family devices.)
To control the auto-negotiation process, the Network
Port Manager generates MII Management Frames to
execute the procedure described below. (See Appen-
dix B, MII Management Registers, for the MII register
bit descriptions.)
The Network Port Manager is held in the IDLE state
while H_RESET is asserted, while the EEPROM is
being read and while the DISPM bit is set. When none
of these conditions are true, the Network Port Manager
proceeds through the following steps:
1. If XPHYRST is set, write to the PHY’s Control Reg-
2. If XPHYRST is not set or after the PHY reset is com-
3. If the PHY’s Auto-Negotiation Ability bit (R1, bit 3) is
4. Otherwise write to the Auto-Negotiation Advertise-
5. Write to the Control Register (R0) to restart Auto-
6. Poll R1 until the Auto-Negotiation Complete bit is
7. Read the Auto-Negotiation Link Partner Ability Reg-
88
ister (R0) to set the Soft Reset bit and cause the
PHY to reset. The Network Port Manager then peri-
odically reads the PHY’s Control Register (R0) until
the reset is complete.
plete, the PHY’s Status Register (R1) is read.
0 or if the XPHYANE bit in the Control2 Register is
0, write to the PHY’s Control Register (R0) to dis-
able auto-negotiation and set the speed and duplex
mode to the values specified by the XPHYSP and
XPHYFD bits in the Control2 Register “and”ed with
the appropriate bits from the PHY's Technology
Ability Field. Then proceed to step 8.
ment Register (R4). Bits A0 to A5 of Technology
Ability field of R4 are taken from bits 15 to 11 in R1.
Bit A6 of the Technology Ability field indicates the
MAC's ability to respond to MAC Control Pause
frames. This bit is set equal to the value of the Ne-
gotiate Pause Ability (NPA) bit in the Flow Control
Register. The Next Page, Acknowledge, and Re-
mote Fault bits are set to 0, and the Selector Field
is set to 00001 to indicate IEEE Std 802.3.
negotiation.
set to 1.
ister (R5). Set the MAC's speed, duplex mode, and
P R E L I M I N A R Y
Am79C976
8. Poll R1 until the Link Status bit is 1. If Link Status is
9. Poll R1 at intervals of about 900 ms until the Link
When Auto-Negotiation is complete, the Network Port
Manager examines the MF Preamble Suppression bit
in PHY register 1. If this bit is set, the Network Port
Manager suppresses preambles on all frames that it
sends until one of the following events occurs:
I A Software or hardware reset occurs.
I The DISPM bit (in CMD3.bit 14 Register) is set.
I Management frame read error occurs.
I The external PHY is disconnected.
A complete bit description of the MII and Auto-
Negotiation registers can be found in Appendix B.
The Network Port Manager is not disabled when the
MDIO pin is held low when the MII Management Inter-
face is idle. If no PHY is connected, reads of the exter-
nal PHY's registers will result in read errors, causing
the MREINT interrupt to be asserted.
Auto-Negotiation With Multiple PHY Devices
The MII Management Interface (MDC and MDIO) can
be used to manage more than one external PHY de-
vice. The external PHY devices may or may not be con-
nected to the Am79C976 controller’s MII bus. For
example, two PHY devices can be connected to the
Am79C976 controller’s MII bus so that the MAC can
communicate over either a twisted-pair cable or a fiber-
optic link. Conversely, several Am79C976 controllers
may share a single integrated circuit that contains sev-
eral PHY devices with separate MII busses but with
only one MII Management bus. In this case, the MII
Management Interface of one Am79C976 controller
could be used to manage PHY devices connected to
different Am79C976 controllers.
If more than one PHY device is connected to the MII
bus, only one PHY device is allowed to be enabled at
any one time. Since the Network Port Manager can not
detect the presence of more than one PHY on the MII
bus, the host CPU is responsible for making sure that
only one PHY is enabled. The host CPU can use the
PHY Access Register to set the Isolate bit in the Con-
trol Register (Register 0, bit 10) of any PHY that needs
to be disabled.
Operation Without MMI Management Interface
The Port Manager normally sets up the speed, duplex
mode, and flow control (pause) ability of the MAC
based on the results of auto-negotiation. However, it is
possible to operate the Am79C976 device with no MII
pause ability to the highest priority mode that is
common to both PHY devices.
not found to be 1 after two polls at 900 ms intervals,
go back to step 1.
Status bit is 0. Go to step 8.
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