AM79C976KI AMD (ADVANCED MICRO DEVICES), AM79C976KI Datasheet - Page 102

• Manufacturer Part Number: AM79C976KI
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C976KI

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / RoHS Status: Not Compliant

I PCI Bus Power Management Interface Specifica-
I RWU (hardware controlled) wake-up
All three wake-up events and both control mechanisms
support wake-up from any power state including D3
OnNow Wake-Up Sequence
The system software enables the PME pin by setting
the PME_EN bit in the PMCSR register (PCI configura-
tion registers, offset 48h, bit 8) to 1. When a Wake-up
event is detected, the Am79C976 device sets the
PME_STATUS bit in the PMCSR register (PCI configu-
ration registers, offset 48h, bit 15). Setting this bit
causes the PME signal to be asserted.
Assertion of the PME signal causes external hardware
to wake up the CPU. The system software then reads
102
tion (OnNow) wake-up
LCMODE_SW
LCMODE_EE
MPPEN_EE
MPPEN_SW
Pattern
PG
Input
Pattern Match RAM (PMR)
PMAT1
Link Change
H_RESET
MPEN_EE
MPEN_SW
PMAT0
PMAT_MODE
Magic Packet
Pattern Match
Link Change
Figure 44. OnNow Functional Diagram
MPDETECT
Data from PCI Bus
P R E L I M I N A R Y
R
S
cold
POR
Am79C976
POR
SET
CLR
POR
Q
Q
(PCI bus power off and clock stopped). Figure 44
shows the relationship between these Wake-up events
and the various outputs used to signal to the external
hardware.
the PMCSR register of every PCI device in the system
to determine which device asserted the PME signal.
When the software determines that the signal came
from the Am79C976 device, it writes to the device’s
PMCSR to put the device into power state D0. The soft-
ware then writes a 0 to the PME_STATUS bit to clear
the bit and turn off the PME signal, and it calls the de-
vice’s software driver to tell it that the device is now in
st ate D0. The s ys tem s oftwa re c an c le ar th e
PME_STATUS bit either before, after, or at the same
time that it puts the device back into the D0 state.
D
D
D
SET
CLR
CLR
CLR
SET
SET
Q
Q
Q
Q
Q
Q
PME_EN_OVR
MPMAT
LCDET
PMAT
LCEVENT
MPMAT
PME_EN
POR
MPINT
LED
WUMI
PME Status
D
R
RWU
SET
CLR
Q
Q
PME_STATUS
PME
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