AM79C976KI AMD (ADVANCED MICRO DEVICES), AM79C976KI Datasheet - Page 132

• Manufacturer Part Number: AM79C976KI
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C976KI

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / RoHS Status: Not Compliant

CMD0: Command0
Offset 048h
132
31-16
14-13
11-9
Bit
15
12
8
7
6
5
4
TX_FAST_SPND
RX_FAST_
UINTCMD
RDMD
TDMD
Name
SPND
VAL1
VAL0
RES
RES
RES
Reserved locations. Written as zeros and read as undefined.
Value bit for byte 1. The value of this bit is written to any bits in the CMD0 register that correspond
to bits in the CMD0[14:8] bit map field that are set to 1.
Reserved locations. Written as zeros and read as undefined.
Receive Demand, when set, causes the Descriptor Management Unit to access the Receive
Descriptor Ring without waiting for the chain poll-time counter to expire.
Reserved locations. Written as zeros and read as undefined.
Transmit Demand, when set, causes the Buffer Management Unit to access the Transmit
Descriptor Ring without waiting for the poll-time counter to elapse. If TXON is not enabled, TDMD
bit will be reset and no Transmit Descriptor Ring access will occur.
If the TXDPOLL bit in CMD2 is set, the host processor must set TDMD each time it is ready for the
Am79C976 device to poll the Transmit Descriptor Ring. When TXDPOLL = 0, setting TDMD
merely hastens the Am79C976 controller’s next access to a Transmit Descriptor Ring Entry.
Value bit for byte 0. The value of this bit is written to any bits in the CMD0 register that correspond
to bits in the CMD0[6:0] bit map field that are set to 1.
User Interrupt Command. UINTCMD can be used by the host to generate an interrupt unrelated to
any network activity. Writing a 1 to this bit causes the UINT bit in the Interrupt Register to be set to
1, which in turn causes INTA to be asserted if interrupts are enabled.
UINTCMD is always read as 0.
Receive Fast Suspend. Setting this bit causes the receiver to suspend its activities as quickly as
possible without stopping in the middle of a frame reception. Setting RX_FAST_SPND does not
stop the DMA controller from transferring frame data from the receive FIFO to host memory.
If a frame is being received at the time that RX_FAST_SPND is set to 1, the reception of that frame
will be completed, but no more frames will be received until RX_FAST_SPND is cleared to 0.
After the receiver has suspended its activity, the RX_SUSPENDED bit in the Status register and
the Suspend Interrupt (SPNDINT) bit in the Interrupt register will be set, which will cause an
interrupt to occur if interrupts are enabled and the SPNDINTEN bit in the Interrupt Enable register
is set.
Transmit Fast Suspend. Setting this bit causes the transmitter to suspend its activities as quickly
as possible without stopping in the middle of a frame transmission. Setting TX_FAST_SPND does
not stop the DMA controller from transferring frame data from host memory to the transmit FIFO.
If a frame is being transmitted at the time that TX_FAST_SPND is set to 1, the transmission of that
frame will be completed, but no more frames will be transmitted until TX_FAST_SPND is cleared
to 0.
After the transmitter has suspended its activity, the TX_SUSPENDED bit in the Status register and
the Suspend Interrupt (SPNDINT) bit in the INT0 register will be set, which will cause an interrupt
to occur if interrupts are enabled and the SPNDINTEN bit in the Interrupt Enable register is set.
Table 42. CMD0: Command0 Register
P R E L I M I N A R Y
Am79C976
CMD0 is a command-style register. All bits in this reg-
ister are cleared to 0 when the RST pin is asserted, be-
fore the serial EEPROM is read, and after a serial
EEPROM read error.
Description
9/14/00