AM79C976KI AMD (ADVANCED MICRO DEVICES), AM79C976KI Datasheet - Page 308

• Manufacturer Part Number: AM79C976KI
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C976KI

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / RoHS Status: Not Compliant

N
O
INDEX-6
Management Data Output Valid
Management Data Setup and Hold
Master Abort . . . . . . . . . . . . . . . . . . . . . .50, 52
Master Bus Interface Unit . . . . . . . . . . . . . . .41
Master Cycle Data Parity Error Response . . .53
Master Initiated Termination . . . . . . . . . . . . .49
MAX_LAT_A
MDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
MDC Waveform . . . . . . . . . . . . . . . . . . . . .281
MDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Media Access Control . . . . . . . . . . . . . . . . . .68
Media Access Management . . . . . . . . . . . . . .69
Media Independent Interface . . . . . . . . . .30, 83
Media Independent Interface (MII) . . . . . .1, 23
Medium Allocation . . . . . . . . . . . . . . . . . . . .69
Memory-Mapped Registers . . . . . . . . . . . . .124
MIB Offset . . . . . . . . . . . . . . . . . . . . . . . . . .124
MII Management Control Register
MII Management Frames . . . . . . . . . . . . . . .84
MII Management Interface . . . . . . . . . . . . . .84
MII Management Registers . . . . . . . . . . . . .B-1
MII Network Status Interface . . . . . . . . . . . .84
MII Receive Frame Tagging . . . . . . . . . . . . .93
MII Receive Interface . . . . . . . . . . . . . . . . . .83
MII Transmit Interface . . . . . . . . . . . . . . . . .83
MIN_GNT_A
Miscellaneous Loopback Features . . . . . . . .82
Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228
Network Interface . . . . . . . . . . . . . . . . . . . . .33
Network Port Manager . . . . . . . . . . . . . . . . .87
Non-Burst Read Transfer . . . . . . . . . . . . . . .43
Non-Burst Write Transfer . . . . . . . . . . . . . . .45
Normal and Tri-State Outputs . . . . . . . . . . .273
OnNow Functional Diagram . . . . . . . . . . . .102
OnNow Wake-Up Sequence . . . . . . . . . . . .102
Operating Ranges . . . . . . . . . . . . . . . . . . . .268
Operation Without MMI Management
Other Data Registers . . . . . . . . . . . . . . . . . .106
Outline of LAPP Flow . . . . . . . . . . . . . . . . .A-2
Output and Float Delay Timing . . . . . . . . . .271
Delay Timing . . . . . . . . . . . . . . . . . . . . . .282
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .282
(Register 0) . . . . . . . . . . . . . . . . . . . . . . . .B-1
Interface . . . . . . . . . . . . . . . . . . . . . . . . . . .88
PCI Maximum Latency Alias Register . .162
PCI Minimum Grant Alias Register . . . .162
P R E L I M I N A R Y
Am79C976
P
Output Tri-state Delay Timing . . . . . . . . . .275
Output Valid Delay Timing . . . . . . . . . . . . .275
PADR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228
PAL function . . . . . . . . . . . . . . . . . . . . . . . . . .3
PAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Parity Error . . . . . . . . . . . . . . . . . . . . . . . . . .26
Parity Error Response . . . . . . . . . . . . . . .40, 52
Pattern Match RAM . . . . . . . . . . . . . . . . . . 105
Pause Count Register . . . . . . . . . . . . . . . . . .163
PCI Base-Class Register Offset 0Bh . . . . . .116
PCI Bus Interface Pins - 3.3 V Signaling . .269
PCI Bus Interface Pins - 5 V Signaling . . . .269
PCI Cache Line Size Register
PCI Capabilities Pointer Register
PCI Capability Identifier Register
PCI Command Register . . . . . . . . . . . . . . . . 113
PCI Command Register Offset 04h . . . . . . .113
PCI Configuration Alias registers . . . . . . . .113
PCI Configuration Registers . . . .108, 113, 247
PCI Configuration Space Layout . . . . . . . .108
PCI Data Register Offset 4Bh . . . . . . . . . . .123
PCI Device ID Register Offset 02h . . . . . . .113
PCI Expansion ROM Base Address
PCI Header Type Register Offset 0Eh . . . . 117
PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . .25
PCI Interrupt Line Register Offset 3Ch . . .120
PCI Interrupt Pin Register Offset 3Dh . . . .120
PCI Latency Timer Register Offset 0Dh . . . 117
PCI MAX_LAT Register Offset 3Fh . . . . . 121
PCI Memory Mapped I/O Base Address
PCI MIN_GNT Register Offset 3Eh . . . . . .120
PCI Next Item Pointer Register
PCI PMCSR Bridge Support Extensions
PCI Power Management Capabilities
PCI Power Management Control/Status
PCI Programming Interface
Offset 0Ch . . . . . . . . . . . . . . . . . . . . . . . . .117
Offset 34h . . . . . . . . . . . . . . . . . . . . . . . . .120
Offset 44h . . . . . . . . . . . . . . . . . . . . . . . . .121
Register Offset 30h . . . . . . . . . . . . . . . . . .119
Register Offset 14h . . . . . . . . . . . . . . . . . .118
Offset 45h . . . . . . . . . . . . . . . . . . . . . . . . .121
Register Offset 4Ah . . . . . . . . . . . . . . . . .123
Register (PMC) Offset 46h . . . . . . . . . . . .121
Register (PMCSR) Offset 48h . . . . . . . . . 122
Register Offset 09h . . . . . . . . . . . . . . . . . .116
Physical Address Register . . . . . . . . . . . .162
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