AM79C976KI AMD (ADVANCED MICRO DEVICES), AM79C976KI Datasheet - Page 186

• Manufacturer Part Number: AM79C976KI
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C976KI

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / RoHS Status: Not Compliant

0
CSR8: Logical Address Filter 0
Bit
31-16
15-0
CSR9: Logical Address Filter 1
Bit
31-16
15-0
CSR10: Logical Address Filter 2
Bit
31-16
186
LADRF[31:16]
MIIPDTINTEMII PHY Detect Transition Inter-
Name
RES
LADRF[15:0]
Name
RES
Name
RES
rupt Enable. If MIIPDTINTE is set
to 1, the MIIPDTINT bit will be
able to set the INTR bit.
Read/Write
DTINTE is set to 0 by H_RESET
and is not affected by S_RESET
or setting the STOP bit.
zeros and read as undefined.
Logical
LADRF-[15:0]. The content of this
register is undefined until loaded
from the initialization block after
the INIT bit in CSR0 has been set
or a direct register write has been
performed on this register.
Read/Write accessible. These
bits are cleared by H_RESET but
are unaffected by S_RESET, or
STOP.
zeros and read as undefined.
Logical Address Filter, LADRF-
[31:16]. The content of this regis-
ter is undefined until loaded from
the initialization block after the
INIT bit in CSR0 has been set or
a direct register write has been
performed on this register.
Read/Write accessible. These
bits are cleared by H_RESET but
are unaffected by S_RESET, or
STOP.
zeros and read as undefined.
Reserved locations. Written as
Reserved locations. Written as
Reserved locations. Written as
Description
Description
Description
Address
accessible.
P R E L I M I N A R Y
Filter,
MIIP-
Am79C976
15-0 LADRF[47:32]Logical
CSR11: Logical Address Filter 3
Bit
31-16 RES
15-0
CSR12: Physical Address Register 0
Note: Bits 15-0 in this register are programmable
through the EEPROM.
Bit
31-16 RES
15-0
LADRF[63:48]
Name
Name
PADR[15:0] Physical
LADRF[47:32]. The content of
this register is undefined until
loaded from the initialization
block after the INIT bit in CSR0
has been set or a direct register
write has been performed on this
register.
Read/Write accessible. These
bits are cleared by H_RESET but
are unaffected by S_RESET, or
STOP.
Logical
LADRF[63:48]. The content of
this register is undefined until
loaded from the initialization
block after the INIT bit in CSR0
has been set or a direct register
write has been performed on this
register.
Read/Write accessible. These
bits are cleared by H_RESET but
are unaffected by S_RESET, or
STOP.
Reserved locations. Written as
zeros and read as undefined.
Reserved locations. Written as
zeros and read as undefined.
PADR[15:0]. The contents of this
register
EEPROM after H_RESET or by
an EEPROM read command
(PREAD, BCR19, bit 14). If the
EEPROM is not present, the con-
tents of this register are unde-
fined.
This register can also be loaded
from the initialization block after
the INIT bit in CSR0 has been set
Description
Description
are
Address
Address
Address
loaded
Register,
9/14/00
Filter,
Filter,
from