AM79C976KI AMD (ADVANCED MICRO DEVICES), AM79C976KI Datasheet - Page 28

• Manufacturer Part Number: AM79C976KI
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C976KI

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / RoHS Status: Not Compliant

Change Detect mode and a Link Change has been de-
tected.
This pin can drive the external system management
logic that causes the CPU to get out of a low power
mode of operation. This pin is implemented for designs
that do not support the PME function.
Three bits that are loaded from the EEPROM into
CSR116 can program the characteristics of this pin:
1. RWU_POL determines the polarity of the RWU sig-
2. If RWU_GATE bit is set, RWU is forced to the high
3. RWU_DRIVER determines whether the output is
The internal power-on-reset signal forces this output
into the high impedance state until after the polarity and
drive type have been determined.
WUMI
Wake-Up Mode Indicator
Open Drain
This output, which is capable of driving an LED, is as-
serted when the device is in Magic Packet mode. It can
be used to drive external logic that switches the device
power source from the main power supply to an auxil-
iary power supply.
VAUX_SENSE
3.3 Vaux Presence Sense
The signal on this pin is logically anded with bit 15 of
the PCI PMC register when the PMC register is read.
This pin should normally be connected to the PCI
3.3 Vaux pin. This allows the PMC register to indicate
that the device is capable of supporting PME from the
D3
power.
CLKSEL0
Clock Select 0
The Am79C976 system clock can either be driven by
an external clock generator connected to the XCLK pin
or by an internal clock generator timed by a 25-MHz
crystal connected between the XTAL1 and XTAL2 pins.
The CLKSEL0 and CLKSEL1 pins select the source of
the system clock and the frequency at which the exter-
nal clock generator must run. In addition, CLKSEL0
and CLKSEL1 determine the frequency of ERCLK, the
external SSRAM clock. Table 1 shows the possible
combinations.
CLKSEL1
Clock Select 1
The Am79C976 system clock can either be driven by
an external clock generator connected to the XCLK pin
28
cold
nal.
impedance state when PG input is LOW.
open drain or totem pole.
state only when the 3.3 Vaux pin is supplying
P R E L I M I N A R Y
Output,
Input
Input
Input
Am79C976
or by an internal clock generator timed by a 25-MHz
crystal connected between the XTAL1 and XTAL2 pins.
The CLKSEL0 and CLKSEL1 pins select the source of
the system clock and the frequency at which the exter-
nal clock generator must run. In addition CLKSEL0 and
CLKSEL1 determine the frequency of ERCLK, the ex-
ternal SSRAM clock. Table 1 shows the possible com-
binations.
CLKSEL2
Clock Select 2
The CLKSEL2 pin must be held low during normal op-
eration.
TEST
Test Reset
The TEST pin must be held low during normal opera-
tion.
XCLK
External Clock Input
The Am79C976 system clock can either be driven by
an external clock generator connected to this pin or by
a 25-MHz crystal connected between the XTAL1 and
XTAL2 pins, depending on the state of the CLKSEL0
and CLKSEL1 pins. When either CLKSEL0 or
CLKSEL1 or both are held high, a 20-, 25-, or
33
shown in Table 1. When CLKSEL0 and CLKSEL1 are
both held low, the XCLK pin should be connected to ei-
ther VSS or VDD.
XTAL1
Crystal
If the CLKSEL0 and CLKSEL1 pins are both held low,
a 25-MHz crystal should be connected between the
XTAL1 pin and the XTAL2 pin. This crystal controls the
frequency of the internal clock-generator circuit.
CLKSEL2 CLKSEL1 CLKSEL0
1
/
3
1
0
0
0
0
-MHz
Table 1. System Clock Selections
clock signal must be applied to XCLK as
X
0
0
1
1
X
0
1
0
1
XTAL1,XT
SOURCE
XCLK, 20
XCLK, 25
33
CLOCK
25-MHz
Crystal,
XCLK,
1
MHz
MHz
AL2
Design Factory
/
3
MHz
Test Only.
ERCLK
9/14/00
(MHz)
87.5
87.5
82.5
90
Input
Input
Input
Input