82P2284BB IDT, Integrated Device Technology Inc, 82P2284BB Datasheet - Page 98

• Manufacturer Part Number: 82P2284BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2284BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Table 55: Related Bit / Register In Chapter 3.20.3
3.20.4 BIT-ORIENTED MESSAGE TRANSMITTER (T1/J1 ONLY)
format in T1/J1 mode.
the F-bit in the ESF format. The six ‘X’s represent the code that is
programmed in the XBOC[5:0] bits. The BOM is transmitted only if the
XBOC[5:0] bits are not all ’One’s.
Table 54: APRM Interpretation
Functional Description
IDT82P2284
A Logic 1 In The Following Bit Position
The Bit Oriented Message (BOM) can only be transmitted in the ESF
The BOM pattern is ‘111111110XXXXXX0’ which occupies the DL of
AUTOPRM
CRBIT
U1BIT
U2BIT
LBBIT
RBIT
Bit
G1
G2
G3
G4
G5
G6
SE
FE
LV
SL
APRM Control
Register
T1/J1 Address (Hex)
07F, 17F, 27F, 37F
Bipolar Violation (BPV) Error / HDB3 Code Violation (CV) Error event ≥ 1
98
Severely Frame Alignment Bit Error event ≥ 1
3.20.5 INBAND LOOPBACK CODE GENERATOR (T1/J1 ONLY)
loopback code in a framed or unframed T1/J1 data stream.
programmed in the CL[1:0] bits and the IBC[7:0] bits respectively. The
code can only be transmitted when the IBCDEN bit is enabled. In framed
mode, which is configured by the IBCDUNFM bit, the bits in all 24 chan-
nels are overwritten with the inband loopback code and the F-bit is not
changed. In unframed mode, which is configured by the IBCDUNFM bit,
all the bits in 24 channels and the F-bit are overwritten with the inband
loopback code.
Table 56: Related Bit / Register In Chapter 3.20.4 & Chapter 3.20.5
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Frame Alignment Bit Error event ≥ 1
The Inband Loopback Code Generator can only transmit inband
The length and the content of the inband loopback code are
IBCDUNFM
XBOC[5:0]
100 < CRC-6 Error event ≤ 319
IBCDEN
10 < CRC-6 Error event ≤ 100
IBC[7:0]
CL[1:0]
5 < CRC-6 Error event ≤ 10
1 < CRC-6 Error event ≤ 5
CRC-6 Error event > 320
Bit
CRC-6 Error event = 1
Buffer Slip event ≥ 1
Interpretation
XIBC Control
XBOC Code
XIBC Code
Register
T1/J1 Address (Hex)
080, 180, 280, 380
075, 175, 275, 375
074, 174, 274, 374
February 25, 2008