82P2284BB IDT, Integrated Device Technology Inc, 82P2284BB Datasheet - Page 72

• Manufacturer Part Number: 82P2284BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2284BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

3.17.1.1 Receive Clock Master Mode
signal on the RSCKn pin and framing pulse on the RSFSn pin to output
the data on each RSDn pin. The signaling bits on the RSIGn pin are per-
channel aligned with the data on the RSDn pin.
is clocked by the RSCKn. The active edge of the RSCKn used to update
the pulse on the RSFSn is determined by the FE bit. The active edge of
the RSCKn used to update the data on the RSDn and RSIGn is deter-
mined by the DE bit. If the FE bit and the DE bit are not equal, the pulse
on the RSFSn is ahead.
bit or the first F-bit of every SF/ESF/T1 DM/SLC-96 multi-frame. In SF
format, the RSFSn can also indicate every second F-bit or the first F-bit
of every second SF multi-frame. All the indications are selected by the
CMFS bit and the ALTIFS bit. The active polarity of the RSFSn is
selected by the FSINV bit.
Clock Master Full T1/J1 mode and Receive Clock Master Fractional T1/
J1 mode.
Receive Clock Master Full T1/J1 Mode
Master mode, the special feature in this mode is that the RSCKn is a
standard 1.544 MHz clock, and the data in the F-bit and all 24 channels
in a standard T1/J1 frame are clocked out by the RSCKn.
Receive Clock Master Fractional T1/J1 Mode
Master mode, the special feature in this mode is that the RSCKn is a
gapped 1.544 MHz clock (no clock signal during the selected position).
1.544
2.048
Mb/s
Mb/s
Functional Description
IDT82P2284
In the Receive Clock Master mode, each link uses its own timing
In the Receive Clock Master mode, the data on the system interface
In the Receive Clock Master mode, the RSFSn can indicate each F-
The Receive Clock Master mode includes two sub-modes: Receive
Besides all the common functions described in the Receive Clock
Besides all the common functions described in the Receive Clock
F
TS0
filler
CH1
TS1
CH2
TS2
Figure 18. T1/J1 To E1 Format Mapping - G.802 Mode
CH14
TS14 TS15 TS16 TS17 TS18
CH15
CH16
filler
CH17
72
The RSCKn is also gapped during the channels or the Bit 8 duration by
selecting the G56K & GAP bits in the Receive Payload Control. The data
in the corresponding gapped duration is a don't care condition.
3.17.1.2 Receive Clock Slave Mode
Mb/s or 2.048 Mb/s. If the system data rate is 1.544 Mb/s, it works in T1/
J1 mode. If the system data rate is 2.048 Mb/s, the received data stream
(1.544 Mb/s) should be mapped to the same rate as the system side,
that is, to work in T1/J1 mode E1 rate. Three kinds of schemes are
provided by selecting the MAP[1:0] bits:
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
The RSCKn is gapped during the F-bit if the FBITGAP bit is set to ‘1’.
In the Receive Clock Slave mode, the system data rate can be 1.544
• T1/J1 Mode E1 Rate per G.802 (refer to Figure 18): Channel 1 to
• T1/J1 Mode E1 Rate per One Filler Every Fourth CH (refer to
• T1/J1 Mode E1 Rate per Continuous CHs (refer to Figure 20):
Channel 15 of Frame N from the device are converted into TS1 to
TS15 of Frame N on the system side; Channel 16 to Channel 24 of
Frame N from the device are converted into TS17 to TS25 of
Frame N on the system side. The F-bit of Frame N from the device
is converted into the first bit of TS26 of Frame (N-1) on the system
side. TS0, TS16, TS27~TS31 and the other 7 bits in TS26 on the
system side are all filled with ‘0’s and they are meaningless.
Figure 19): One dummy byte is inserted on the system side before
3 bytes of Frame N from the device are converted. This process
repeats 8 times and the conversion of Frame N of 1.544 Mb/s data
rate to 2.048 Mb/s data rate is completed. However, the F-bit of
Frame N of the 1.544 Mb/s data rate is inserted as the 8th bit of
Frame N of the 2.048 Mb/s data rate. The dummy bytes are filled
with all ‘0’s and they are meaningless.
Channel 1 to Channel 24 of Frame N from the device are con-
verted into TS1 to TS24 of Frame N on the system side. The F-bit
of Frame N from the device is converted into the 8th bit of Frame N
on the system side. The first 7 bits and TS25 to TS31 on the sys-
tem side are all filled with ‘0’s and they are meaningless.
CH23
TS24 TS25
CH24
the 1st bit
F
TS26 TS27~TS31
CH1
filler
CH2
filler
February 25, 2008
TS0
filler
CH23
TS1