82P2284BB IDT, Integrated Device Technology Inc, 82P2284BB Datasheet - Page 83

• Manufacturer Part Number: 82P2284BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2284BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

arranged by setting the channel offset. The data to different links from
one multiplexed bus must be shifted at a different channel offset to avoid
data mixing.
pin and the framing pulse on the MTSFS pin are provided by the system
side and common to all four links. The signaling bits on the MTSIGA
(MTSIGB) pin are per-channel aligned with the corresponding data on
the MTSDA (MTSDB) pin.
clocked by the MTSCK. The active edge of the MTSCK used to sample
the pulse on the MTSFS is determined by the FE bit. The active edge of
the MTSCK used to sample the data on the MTSDA (MTSDB) and
MTSIGA (MTSIGB) is determined by the DE bit. The FE bit and the DE
bit of the four links should be set to the same value respectively. If the
FE bit and the DE bit are not equal, the pulse on the MTSFS is ahead.
The MTSCK can be selected by the CMS bit to be the same rate as the
data rate on the system side (8.192 MHz) or double the data rate
(16.384 MHz). The CMS bit of the four links should be set to the same
value. If the speed of the MTSCK is double the data rate, there will be
two active edges in one bit duration. In this case, the EDGE bit deter-
Functional Description
IDT82P2284
In the Transmit Multiplexed mode, the timing signal on the MTSCK
In the Transmit Multiplexed mode, the data on the system interface is
Transmit Clock Slave mode / Transmit Multiplexed mode:
Transmit Clock Master mode:
TSFSn / MTSFS
TSCKn / MTSCK
TSDn / MTSDA(B)
TSFSn / MTSFS
TSCKn / MTSCK
TSDn / MTSDA(B)
Figure 28. No Offset When FE = 1 & DE = 1 In Transmit Path
Bit 1 of TS0 (E1)
Bit 1 of TS0 (E1)
F-bit (T1/J1)
F-bit (T1/J1)
FE = 1, DE = 1
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mines the active edge to sample the data on the MTSDA (MTSDB) and
MTSIGA (MTSIGB) pins. The pulse on the MTSFS pin is always
sampled on its first active edge.
bit of the first link or the first F-bit of every SF/ESF/T1 DM/SLC-96 multi-
frame of the first link. The indications are selected by the FSTYP bit. The
active polarity of the MTSFS is selected by the FSINV bit. The FSTYP
bit and the FSINV bit of the four links should be set to the same value. If
the pulse on the MTSFS pin is not an integer multiple of 125 µs, this
detection will be indicated by the TCOFAI bit. If the TCOFAE bit is
enabled, an interrupt will be reported by the INT pin when the TCOFAI
bit is ‘1’.
3.18.1.4 Offset
modes. The offset is between the framing pulse on the TSFSn/MTSFS
pin and the start of the corresponding frame input on the TSDn/
MTSDA(MTSDB)
MTSIGA(MTSIGB) pin are always per-channel aligned with the data on
the TSDn/MTSDA(MTSDB) pin.
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Bit 1 of CH1(T1/J1)
Bit 1 of CH1(T1/J1)
In the Transmit Multiplexed mode, the MTSFS can indicate each F-
Bit offset and channel offset are both supported in all the operating
Figure 28 to Figure 31 show the base line without offset.
Bit 2 of TS0 (E1)
Bit 2 of TS0 (E1)
pin.
The
Bit 2 (T1/J1)
Bit 2 (T1/J1)
Bit 3 (E1)
Bit 3 (E1)
signaling
bits
February 25, 2008
on
the
TSIGn/