82P2284BB IDT, Integrated Device Technology Inc, 82P2284BB Datasheet - Page 322
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82P2284BB
Manufacturer Part Number
82P2284BB
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.82P2284BB.pdf
(363 pages)
Specifications of 82P2284BB
Screening Level
Industrial
Mounting
Surface Mount
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
82P2284BBG
Manufacturer:
NS/TI
Quantity:
5 705
- Current page: 322 of 363
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E1 PMON Interrupt Indication 1 (0C6H, 1C6H, 2C6H, 3C6H)
LCVOVI:
E1 TPLC / RPLC / PRGD Test Configuration (0C7H, 1C7H, 2C7H, 3C7H)
PRBSMODE[1:0]:
PRBSDIR:
TESTEN:
E1 TPLC Access Status (0C8H, 1C8H, 2C8H, 3C8H)
BUSY:
Programming Information
IDT82P2284
Bit Name
Bit Name
Bit Name
= 0: The PMON indirect LCV Counter Mapping registers have not overflowed.
= 1: The PMON indirect LCV Counter Mapping registers have overflowed.
This bit will be cleared if a ’1’ is written to it.
These two bits select one mode to extract/replace the data for the PRBS Generator/Detector.
= 00: The unframed mode is selected. All 32 timeslots are extracted/replaced and the per-timeslot configuration in the TEST bit (b6, E1-ID-41~4FH
& 51~5FH) is ignored.
= 01: The 8-bit-based mode is selected. The received data will only be extracted/replaced on the timeslot configured by the TEST bit (b6, E1-ID-
41~4FH & 51~5FH).
= 10: The 7-bit-based mode is selected. The received data will only be extracted/replaced on the 7 MSB of the timeslot configured by the TEST bit
(b6, E1-ID-41~4FH & 51~5FH).
= 11: Reserved.
= 0: The pattern in the PRBS Generator/Detector is generated in the transmit path and is detected in the receive path.
= 1: The pattern in the PRBS Generator/Detector is generated in the receive path and is detected in the transmit path.
A transition from ‘0’ to ‘1’ on this bit initiates the PRBS Generator/Detector.
= 0: No reading or writing operation on the indirect registers.
= 1: An internal indirect register is being accessed. Any new operation on the internal indirect register is not allowed.
Default
Default
Default
Bit No.
Bit No.
Bit No.
Type
Type
Type
7
7
7
6
6
6
Reserved
5
5
5
Reserved
Reserved
4
4
4
322
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
PRBSMODE1
R/W
3
3
0
3
PRBSMODE0
R/W
2
2
0
2
PRBSDIR
R/W
1
1
0
1
February 25, 2008
TESTEN
LCVOVI
BUSY
R/W
R
R
0
0
0
0
0
0
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