KS8993F A5 Micrel Inc, KS8993F A5 Datasheet - Page 65

• Manufacturer Part Number: KS8993F A5
• Manufacturer: Micrel Inc

Specifications of KS8993F A5

• Number Of Primary Switch Ports: 3
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 1.89/3.465V
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Not Compliant

KS8993F
4.3
Register 64 (0x40): PHY Address
Register 65 (0x41): Center Side Status
August 26, 2004
Bit
7–5
4
3
2
1
0
Bit
7
6
5–3
2
1
0
Media Converter Registers
Name
Reserved
Addr4
Addr3
Addr2
Addr1
Addr0
Name
BUSY
Vendor mode
Reserved
Option b
Option a
Request
R/W
RO
R/W
R/W
R/W
R/W
R/W
R/W
RO
R/W
RO
R/W
R/W
RO
Description
N/A
For Center side MC mode, these bits are port 1’s PHY address.
For Terminal side MC mode, these bits are fixed at 0x01h for port 1’s
PHY address.
Notes
port
0x02h.
Description
1 = indicate MC loop back mode inprogress, or receive reply
1 = non special vendor mode
0 = special vendor mode (compare My & LNK Partner Vendor
Reserved
1 = clear status bits S6 to S10 to zero on Terminal MC side
0 = normal operation – supporting option b
1 = disable “Indicate Center MC Condition” frame
0 = enable “Indicate Center MC condition” frame
1 = indicate change of status/value in registers # 0x50h, 0x51h,
0x58h, 0x59h, 0x5Dh, 0x5Eh, 0x5Fh. This bit is self-cleared after a
read.
0 = exclude the above situations
0 = exclude the above situations
0 0000 : N/A
0 0001 : Port 1’s PHY address is 0x01h
0 0011 : Port 1’s PHY address is 0x03h
other values : N/A
(1) If pins [MCHS,MCCS] = [0,1], a write to these bits with port 1’s
(2) If pins [MCHS,MCCS] = [0,1], the MIIM bus can only access
(3) If pins [MCHS, MCCS] != [0,1], the MIIM bus will access port 1
Info = 0x009099h)
frame/timeout is pending
PHY address is required to enable port 1 and start the Center
side MC.
using PHY address 0x01h and port 2 using PHY address
1.
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Revision 1.0
Defaul
t
000
0
0
0
0
1
Defaul
t
0
0
000
0
0
0
Micrel