KS8993F A5 Micrel Inc, KS8993F A5 Datasheet - Page 37

• Manufacturer Part Number: KS8993F A5
• Manufacturer: Micrel Inc

Specifications of KS8993F A5

• Number Of Primary Switch Ports: 3
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 1.89/3.465V
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Not Compliant

KS8993F
The Serial Management Interface is the KS8993F non-standard MIIM interface that provides access to all KS8993F
configuration registers. This interface allows an external device to completely monitor and control the states of the
KS8993F.
The SMI interface consists of the following:
The following table depicts the Serial Management Interface frame format.
For the KS8993F, SMI register access is selected when bit 2 of the PHY address is set to ‘1’. PHY address bits [1:0]
are not defined for SMI register access, and hence can be set to either 0’s or 1’s in read/write operation.
To access the KS8993F registers 0-127 (0x00 – 0x7F), the following applies:
SMI register access is the same as the MIIM register access, except for the register access requirements presented in
this section.
2.9
2.9.1 Port Mirroring Support
KS8993F supports “Port Mirroring” comprehensively as:
August 26, 2004
Advanced Switch Function
Write
Read
A physical connection that incorporates the data line (MDIO) and the clock line (MDC).
A specific protocol that operates across the aforementioned physical connection that allows an external
controller to communicate with the KS8993F device.
Access to all KS8993F configuration registers. Registers access includes the Global, Port and Advanced
Control Registers 0-127 (0x00 – 0x7F), and indirect access to the standard MIIM registers [0:5].
PHYAD[4:3] and REGAD[4:0] are concatenated to form the 7-bits address.
i.e., {PHYAD[4:3], REGAD[4:0]} = bits [6:0] of the 7-bits address.
Registers are 8 data bits wide. For read operation, data bits [15:8] are read back as 0’s. For write
operation, data bits [15:8] are not defined, and hence can be set to either 0’s or 1’s.
Preamble
32 1’s
32 1’s
Start of
Frame
Table 6: Serial Management Interface (SMI) frame format
01
01
Read/Write
OP Code
10
01
Bits [4:0]
Address
RR1xx
RR1xx
PHY
- 37 -
Bits [4:0]
Address
RRRRR
RRRRR
REG
TA
Z0
10
0000_0000_DDDD_DDDD
xxxx_xxxx_DDDD_DDDD
Bits [15:0]
Data
Idle
Revision 1.0
Z
Z
Micrel